openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43 Let the effective address (EA) be the sum (RA|0)+ D.
  44 The byte in storage addressed by EA is loaded into
  45 RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Load Byte and Zero with Update
  68
  69 D-Form
  70
  71 * lbzu RT,D(RA)
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + EXTS(D)
  76     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  77     RA <- EA
  78
  79 Special Registers Altered:
  80
  81     None
  82
  83 # Load Byte and Zero with Update Indexed
  84
  85 X-Form
  86
  87 * lbzux RT,RA,RB
  88
  89 Pseudo-code:
  90
  91     EA <- (RA) + (RB)
  92     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  93     RA <- EA
  94
  95 Description:Let the effective address (EA) be the sum (RA)+ (RB).
  96 The byte in storage addressed by EA is loaded into
  97 RT56:63. RT0:55 are set to 0.
  98 EA is placed into register RA.
  99 If RA=0 or RA=RT, the instruction form is invalid.
 100
 101 Special Registers Altered:
 102
 103     None
 104
 105 # Load Halfword and Zero
 106
 107 D-Form
 108
 109 * lhz RT,D(RA)
 110
 111 Pseudo-code:
 112
 113     b <- (RA|0)
 114     EA <- b + EXTS(D)
 115     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 116
 117 Special Registers Altered:
 118
 119     None
 120
 121 # Load Halfword and Zero Indexed
 122
 123 X-Form
 124
 125 * lhzx RT,RA,RB
 126
 127 Pseudo-code:
 128
 129     b <- (RA|0)
 130     EA <- b + (RB)
 131     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 132
 133 Special Registers Altered:
 134
 135     None
 136
 137 # Load Halfword and Zero with Update
 138
 139 D-Form
 140
 141 * lhzu RT,D(RA)
 142
 143 Pseudo-code:
 144
 145     EA <- (RA) + EXTS(D)
 146     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 147     RA <- EA
 148
 149 Special Registers Altered:
 150
 151     None
 152
 153 # Load Halfword and Zero with Update Indexed
 154
 155 X-Form
 156
 157 * lhzux RT,RA,RB
 158
 159 Pseudo-code:
 160
 161     EA <- (RA) + (RB)
 162     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 163     RA <- EA
 164
 165 Special Registers Altered:
 166
 167     None
 168
 169 # Load Halfword Algebraic
 170
 171 D-Form
 172
 173 * lha RT,D(RA)
 174
 175 Pseudo-code:
 176
 177     b <- (RA|0)
 178     EA <- b + EXTS(D)
 179     RT <- EXTS(MEM(EA, 2))
 180
 181 Special Registers Altered:
 182
 183     None
 184
 185 # Load Halfword Algebraic Indexed
 186
 187 X-Form
 188
 189 * lhax RT,RA,RB
 190
 191 Pseudo-code:
 192
 193     b <- (RA|0)
 194     EA <- b + (RB)
 195     RT <- EXTS(MEM(EA, 2))
 196
 197 Special Registers Altered:
 198
 199     None
 200
 201 # Load Halfword Algebraic with Update
 202
 203 D-Form
 204
 205 * lhau RT,D(RA)
 206
 207 Pseudo-code:
 208
 209     EA <- (RA) + EXTS(D)
 210     RT <- EXTS(MEM(EA, 2))
 211     RA <- EA
 212
 213 Special Registers Altered:
 214
 215     None
 216
 217 # Load Halfword Algebraic with Update Indexed
 218
 219 X-Form
 220
 221 * lhaux RT,RA,RB
 222
 223 Pseudo-code:
 224
 225     EA <- (RA) + (RB)
 226     RT <- EXTS(MEM(EA, 2))
 227     RA <- EA
 228
 229 Special Registers Altered:
 230
 231     None
 232
 233 # Load Word and Zero
 234
 235 D-Form
 236
 237 * lwz RT,D(RA)
 238
 239 Pseudo-code:
 240
 241     b <- (RA|0)
 242     EA <- b + EXTS(D)
 243     RT <- [0] * 32 || MEM(EA, 4)
 244
 245 Special Registers Altered:
 246
 247     None
 248
 249 # Load Word and Zero Indexed
 250
 251 X-Form
 252
 253 * lwzx RT,RA,RB
 254
 255 Pseudo-code:
 256
 257     b <- (RA|0)
 258     EA <- b + (RB)
 259     RT <- [0] * 32 || MEM(EA, 4)
 260
 261 Special Registers Altered:
 262
 263     None
 264
 265 # Load Word and Zero with Update
 266
 267 D-Form
 268
 269 * lwzu RT,D(RA)
 270
 271 Pseudo-code:
 272
 273     EA <- (RA) + EXTS(D)
 274     RT <- [0]*32 || MEM(EA, 4)
 275     RA <- EA
 276
 277 Special Registers Altered:
 278
 279     None
 280
 281 # Load Word and Zero with Update Indexed
 282
 283 X-Form
 284
 285 * lwzux RT,RA,RB
 286
 287 Pseudo-code:
 288
 289     EA <- (RA) + (RB)
 290     RT <- [0] * 32 || MEM(EA, 4)
 291     RA <- EA
 292
 293 Special Registers Altered:
 294
 295     None
 296
 297 # Load Word Algebraic
 298
 299 DS-Form
 300
 301 * lwa RT,DS(RA)
 302
 303 Pseudo-code:
 304
 305     b <- (RA|0)
 306     EA <- b + EXTS(DS || 0b00)
 307     RT <- EXTS(MEM(EA, 4))
 308
 309 Special Registers Altered:
 310
 311     None
 312
 313 # Load Word Algebraic Indexed
 314
 315 X-Form
 316
 317 * lwax RT,RA,RB
 318
 319 Pseudo-code:
 320
 321     b <- (RA|0)
 322     EA <- b + (RB)
 323     RT <- EXTS(MEM(EA, 4))
 324
 325 Special Registers Altered:
 326
 327     None
 328
 329 # Load Word Algebraic with Update Indexed
 330
 331 X-Form
 332
 333 * lwaux RT,RA,RB
 334
 335 Pseudo-code:
 336
 337     EA <- (RA) + (RB)
 338     RT <- EXTS(MEM(EA, 4))
 339     RA <- EA
 340
 341 Special Registers Altered:
 342
 343     None
 344
 345 # Load Doubleword
 346
 347 DS-Form
 348
 349 * ld RT,DS(RA)
 350
 351 Pseudo-code:
 352
 353     b <- (RA|0)
 354     EA <- b + EXTS(DS || 0b00)
 355     RT <- MEM(EA, 8)
 356
 357 Special Registers Altered:
 358
 359     None
 360
 361 # Load Doubleword Indexed
 362
 363 X-Form
 364
 365 * ldx RT,RA,RB
 366
 367 Pseudo-code:
 368
 369     b <- (RA|0)
 370     EA <- b + (RB)
 371     RT <- MEM(EA, 8)
 372
 373 Special Registers Altered:
 374
 375     None
 376
 377 # Load Doubleword with Update Indexed
 378
 379 DS-Form
 380
 381 * ldu RT,DS(RA)
 382
 383 Pseudo-code:
 384
 385     EA <- (RA) + EXTS(DS || 0b00)
 386     RT <- MEM(EA, 8)
 387     RA <- EA
 388
 389 Special Registers Altered:
 390
 391     None
 392
 393 # Load Doubleword with Update Indexed
 394
 395 X-Form
 396
 397 * ldux RT,RA,RB
 398
 399 Pseudo-code:
 400
 401     EA <- (RA) + (RB)
 402     RT <- MEM(EA, 8)
 403     RA <- EA
 404
 405 Special Registers Altered:
 406
 407     None
 408
 409 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 410
 411 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 412 <!-- doubleword in storage addressed by EA. -->
 413
 414 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 415 <!-- updated with the effective address. For these forms, the following rules apply. -->
 416
 417 <!-- If RA!=0, the effective address is placed into register RA. -->
 418
 419 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 420 <!-- and then EA is placed into RA (RS). -->
 421
 422 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 423
 424 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 425
 426 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 427 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 428 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 429 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 430 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 431 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 432 <!-- by EA. -->
 433
 434 # Load Quadword
 435
 436 DQ-Form
 437
 438 * lq RTp,DQ(RA)
 439
 440 Pseudo-code:
 441
 442     b <- (RA|0)
 443     EA <- b + EXTS(DQ || 0b0000)
 444     RTp <- MEM(EA, 16)
 445
 446 Special Registers Altered:
 447
 448     None
 449
 450 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 451
 452 # Load Halfword Byte-Reverse Indexed
 453
 454 X-Form
 455
 456 * lhbrx RT,RA,RB
 457
 458 Pseudo-code:
 459
 460     b <- (RA|0)
 461     EA <- b + (RB)
 462     load_data <- MEM(EA, 2)
 463     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 464
 465 Special Registers Altered:
 466
 467     None
 468
 469 # Load Word Byte-Reverse Indexed
 470
 471 X-Form
 472
 473 * lwbrx RT,RA,RB
 474
 475 Pseudo-code:
 476
 477     b <- (RA|0)
 478     EA <- b + (RB)
 479     load_data <- MEM(EA, 4)
 480     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 481                     || load_data[8:15]  || load_data[0:7])
 482
 483 Special Registers Altered:
 484
 485     None
 486
 487
 488 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 489
 490 # Load Doubleword Byte-Reverse Indexed
 491
 492 X-Form
 493
 494 * ldbrx RT,RA,RB
 495
 496 Pseudo-code:
 497
 498     b <- (RA|0)
 499     EA <- b + (RB)
 500     load_data <- MEM(EA, 8)
 501     RT <- (load_data[56:63] || load_data[48:55]
 502         || load_data[40:47] || load_data[32:39]
 503         || load_data[24:31] || load_data[16:23]
 504         || load_data[8:15]  || load_data[0:7])
 505
 506 Special Registers Altered:
 507
 508     None
 509
 510 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 511
 512 # Load Multiple Word
 513
 514 DQ-Form
 515
 516 * lmw RT,D(RA)
 517
 518 Pseudo-code:
 519
 520     b <- (RA|0)
 521     EA <- b + EXTS(D)
 522     r <- RT[0:63]
 523     do while r <=  31
 524         GPR(r) <- [0]*32 || MEM(EA, 4)
 525         r <- r + 1
 526         EA <- EA + 4
 527
 528 Special Registers Altered:
 529
 530     None
 531