openpower/isa/fixedload.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero
  30
  31 D-Form
  32
  33 * lbz RT,D(RA)
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + EXTS(D)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum (RA|0)+ D.
  44     The byte in storage addressed by EA is loaded into
  45     RT[56:63]. RT[0:55] are set to 0.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Load Byte and Zero Indexed
  52
  53 X-Form
  54
  55 * lbzx RT,RA,RB
  56
  57 Pseudo-code:
  58
  59     b <- (RA|0)
  60     EA <- b + (RB)
  61     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum
  66     (RA|0)+ (RB). The byte in storage addressed by EA is
  67     loaded into RT[56:63] . RT[0:55] are set to 0.
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Byte and Zero with Update
  74
  75 D-Form
  76
  77 * lbzu RT,D(RA)
  78
  79 Pseudo-code:
  80
  81     EA <- (RA) + EXTS(D)
  82     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  83     RA <- EA
  84
  85 Description:
  86
  87     Let the effective address (EA) be the sum (RA)+ D. The
  88     byte in storage addressed by EA is loaded into RT[56:63].
  89     RT[0:55] are set to 0.
  90
  91     EA is placed into register RA.
  92
  93     If RA=0 or RA=RT, the instruction form is invalid.
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Byte and Zero with Update Indexed
 100
 101 X-Form
 102
 103 * lbzux RT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA) + (RB)
 108     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
 109     RA <- EA
 110
 111 Description:
 112
 113     Let the effective address (EA) be the sum (RA)+ (RB).
 114     The byte in storage addressed by EA is loaded into
 115     RT[56:63]. RT[0:55] are set to 0.
 116
 117     EA is placed into register RA.
 118
 119     If RA=0 or RA=RT, the instruction form is invalid.
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Load Halfword and Zero
 126
 127 D-Form
 128
 129 * lhz RT,D(RA)
 130
 131 Pseudo-code:
 132
 133     b <- (RA|0)
 134     EA <- b + EXTS(D)
 135     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 136
 137 Description:
 138
 139     Let the effective address (EA) be the sum (RA|0)+ D.
 140     The halfword in storage addressed by EA is loaded into
 141     RT[48:63]. RT[0:47] are set to 0.
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Halfword and Zero Indexed
 148
 149 X-Form
 150
 151 * lhzx RT,RA,RB
 152
 153 Pseudo-code:
 154
 155     b <- (RA|0)
 156     EA <- b + (RB)
 157     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 158
 159 Description:
 160
 161     Let the effective address (EA) be the sum
 162     (RA|0)+ (RB). The halfword in storage addressed by
 163     EA is loaded into RT 48:63. RT 0:47 are set to 0.
 164
 165 Special Registers Altered:
 166
 167     None
 168
 169 # Load Halfword and Zero with Update
 170
 171 D-Form
 172
 173 * lhzu RT,D(RA)
 174
 175 Pseudo-code:
 176
 177     EA <- (RA) + EXTS(D)
 178     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 179     RA <- EA
 180
 181 Description:
 182
 183     Let the effective address (EA) be the sum (RA)+ D. The
 184     halfword in storage addressed by EA is loaded into
 185     RT[48:63]. RT[0:47] are set to 0.
 186
 187     EA is placed into register RA.
 188
 189     If RA=0 or RA=RT, the instruction form is invalid.
 190
 191 Special Registers Altered:
 192
 193     None
 194
 195 # Load Halfword and Zero with Update Indexed
 196
 197 X-Form
 198
 199 * lhzux RT,RA,RB
 200
 201 Pseudo-code:
 202
 203     EA <- (RA) + (RB)
 204     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 205     RA <- EA
 206
 207 Description:
 208
 209     Let the effective address (EA) be the sum (RA)+ (RB).
 210     The halfword in storage addressed by EA is loaded into
 211     RT[48:63]. RT[0:47] are set to 0.
 212
 213     EA is placed into register RA.
 214
 215     If RA=0 or RA=RT, the instruction form is invalid.
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Halfword Algebraic
 222
 223 D-Form
 224
 225 * lha RT,D(RA)
 226
 227 Pseudo-code:
 228
 229     b <- (RA|0)
 230     EA <- b + EXTS(D)
 231     RT <- EXTS(MEM(EA, 2))
 232
 233 Description:
 234
 235     Let the effective address (EA) be the sum (RA|0)+ D.
 236     The halfword in storage addressed by EA is loaded into
 237     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 238     loaded halfword.
 239
 240 Special Registers Altered:
 241
 242     None
 243
 244 # Load Halfword Algebraic Indexed
 245
 246 X-Form
 247
 248 * lhax RT,RA,RB
 249
 250 Pseudo-code:
 251
 252     b <- (RA|0)
 253     EA <- b + (RB)
 254     RT <- EXTS(MEM(EA, 2))
 255
 256 Description:
 257
 258     Let the effective address (EA) be the sum
 259     (RA|0)+ (RB). The halfword in storage addressed by
 260     EA is loaded into RT[48:63] . RT[0:47] are filled with a copy
 261     of bit 0 of the loaded halfword.
 262
 263 Special Registers Altered:
 264
 265     None
 266
 267 # Load Halfword Algebraic with Update
 268
 269 D-Form
 270
 271 * lhau RT,D(RA)
 272
 273 Pseudo-code:
 274
 275     EA <- (RA) + EXTS(D)
 276     RT <- EXTS(MEM(EA, 2))
 277     RA <- EA
 278
 279 Description:
 280
 281     Let the effective address (EA) be the sum (RA)+ D. The
 282     halfword in storage addressed by EA is loaded into
 283     RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
 284     loaded halfword.
 285
 286     EA is placed into register RA.
 287
 288     If RA=0 or RA=RT, the instruction form is invalid.
 289
 290 Special Registers Altered:
 291
 292     None
 293
 294 # Load Halfword Algebraic with Update Indexed
 295
 296 X-Form
 297
 298 * lhaux RT,RA,RB
 299
 300 Pseudo-code:
 301
 302     EA <- (RA) + (RB)
 303     RT <- EXTS(MEM(EA, 2))
 304     RA <- EA
 305
 306 Description:
 307
 308     Let the effective address (EA) be the sum (RA)+ (RB).
 309     The halfword in storage addressed by EA is loaded into
 310     RT48:63. RT 0:47 are filled with a copy of bit 0 of the
 311     loaded halfword.
 312
 313     EA is placed into register RA.
 314
 315     If RA=0 or RA=RT, the instruction form is invalid.
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Load Word and Zero
 322
 323 D-Form
 324
 325 * lwz RT,D(RA)
 326
 327 Pseudo-code:
 328
 329     b <- (RA|0)
 330     EA <- b + EXTS(D)
 331     RT <- [0] * 32 || MEM(EA, 4)
 332
 333 Special Registers Altered:
 334
 335     None
 336
 337 # Load Word and Zero Indexed
 338
 339 X-Form
 340
 341 * lwzx RT,RA,RB
 342
 343 Pseudo-code:
 344
 345     b <- (RA|0)
 346     EA <- b + (RB)
 347     RT <- [0] * 32 || MEM(EA, 4)
 348
 349 Special Registers Altered:
 350
 351     None
 352
 353 # Load Word and Zero with Update
 354
 355 D-Form
 356
 357 * lwzu RT,D(RA)
 358
 359 Pseudo-code:
 360
 361     EA <- (RA) + EXTS(D)
 362     RT <- [0]*32 || MEM(EA, 4)
 363     RA <- EA
 364
 365 Special Registers Altered:
 366
 367     None
 368
 369 # Load Word and Zero with Update Indexed
 370
 371 X-Form
 372
 373 * lwzux RT,RA,RB
 374
 375 Pseudo-code:
 376
 377     EA <- (RA) + (RB)
 378     RT <- [0] * 32 || MEM(EA, 4)
 379     RA <- EA
 380
 381 Special Registers Altered:
 382
 383     None
 384
 385 # Load Word Algebraic
 386
 387 DS-Form
 388
 389 * lwa RT,DS(RA)
 390
 391 Pseudo-code:
 392
 393     b <- (RA|0)
 394     EA <- b + EXTS(DS || 0b00)
 395     RT <- EXTS(MEM(EA, 4))
 396
 397 Special Registers Altered:
 398
 399     None
 400
 401 # Load Word Algebraic Indexed
 402
 403 X-Form
 404
 405 * lwax RT,RA,RB
 406
 407 Pseudo-code:
 408
 409     b <- (RA|0)
 410     EA <- b + (RB)
 411     RT <- EXTS(MEM(EA, 4))
 412
 413 Special Registers Altered:
 414
 415     None
 416
 417 # Load Word Algebraic with Update Indexed
 418
 419 X-Form
 420
 421 * lwaux RT,RA,RB
 422
 423 Pseudo-code:
 424
 425     EA <- (RA) + (RB)
 426     RT <- EXTS(MEM(EA, 4))
 427     RA <- EA
 428
 429 Special Registers Altered:
 430
 431     None
 432
 433 # Load Doubleword
 434
 435 DS-Form
 436
 437 * ld RT,DS(RA)
 438
 439 Pseudo-code:
 440
 441     b <- (RA|0)
 442     EA <- b + EXTS(DS || 0b00)
 443     RT <- MEM(EA, 8)
 444
 445 Special Registers Altered:
 446
 447     None
 448
 449 # Load Doubleword Indexed
 450
 451 X-Form
 452
 453 * ldx RT,RA,RB
 454
 455 Pseudo-code:
 456
 457     b <- (RA|0)
 458     EA <- b + (RB)
 459     RT <- MEM(EA, 8)
 460
 461 Special Registers Altered:
 462
 463     None
 464
 465 # Load Doubleword with Update Indexed
 466
 467 DS-Form
 468
 469 * ldu RT,DS(RA)
 470
 471 Pseudo-code:
 472
 473     EA <- (RA) + EXTS(DS || 0b00)
 474     RT <- MEM(EA, 8)
 475     RA <- EA
 476
 477 Special Registers Altered:
 478
 479     None
 480
 481 # Load Doubleword with Update Indexed
 482
 483 X-Form
 484
 485 * ldux RT,RA,RB
 486
 487 Pseudo-code:
 488
 489     EA <- (RA) + (RB)
 490     RT <- MEM(EA, 8)
 491     RA <- EA
 492
 493 Special Registers Altered:
 494
 495     None
 496
 497 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
 498
 499 <!-- The contents of register RS are stored into the byte, halfword, word, or -->
 500 <!-- doubleword in storage addressed by EA. -->
 501
 502 <!-- Many of the Store instructions have an “update” form, in which register RA is -->
 503 <!-- updated with the effective address. For these forms, the following rules apply. -->
 504
 505 <!-- If RA!=0, the effective address is placed into register RA. -->
 506
 507 <!-- If RS=RA, the contents of register RS are copied to the target storage element -->
 508 <!-- and then EA is placed into RA (RS). -->
 509
 510 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
 511
 512 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 513
 514 <!-- For lq, the quadword in storage addressed by EA is loaded into an even-odd pair -->
 515 <!-- of GPRs as follows. In Big-Endian mode, the even-numbered GPR is loaded with -->
 516 <!-- the doubleword from storage addressed by EA and the odd-numbered GPR is loaded -->
 517 <!-- with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered -->
 518 <!-- GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 -->
 519 <!-- and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed -->
 520 <!-- by EA. -->
 521
 522 # Load Quadword
 523
 524 DQ-Form
 525
 526 * lq RTp,DQ(RA)
 527
 528 Pseudo-code:
 529
 530     b <- (RA|0)
 531     EA <- b + EXTS(DQ || 0b0000)
 532     RTp <- MEM(EA, 16)
 533
 534 Special Registers Altered:
 535
 536     None
 537
 538 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 539
 540 # Load Halfword Byte-Reverse Indexed
 541
 542 X-Form
 543
 544 * lhbrx RT,RA,RB
 545
 546 Pseudo-code:
 547
 548     b <- (RA|0)
 549     EA <- b + (RB)
 550     load_data <- MEM(EA, 2)
 551     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 552
 553 Special Registers Altered:
 554
 555     None
 556
 557 # Load Word Byte-Reverse Indexed
 558
 559 X-Form
 560
 561 * lwbrx RT,RA,RB
 562
 563 Pseudo-code:
 564
 565     b <- (RA|0)
 566     EA <- b + (RB)
 567     load_data <- MEM(EA, 4)
 568     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 569                     || load_data[8:15]  || load_data[0:7])
 570
 571 Special Registers Altered:
 572
 573     None
 574
 575
 576 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 577
 578 # Load Doubleword Byte-Reverse Indexed
 579
 580 X-Form
 581
 582 * ldbrx RT,RA,RB
 583
 584 Pseudo-code:
 585
 586     b <- (RA|0)
 587     EA <- b + (RB)
 588     load_data <- MEM(EA, 8)
 589     RT <- (load_data[56:63] || load_data[48:55]
 590         || load_data[40:47] || load_data[32:39]
 591         || load_data[24:31] || load_data[16:23]
 592         || load_data[8:15]  || load_data[0:7])
 593
 594 Special Registers Altered:
 595
 596     None
 597
 598 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 599
 600 # Load Multiple Word
 601
 602 DQ-Form
 603
 604 * lmw RT,D(RA)
 605
 606 Pseudo-code:
 607
 608     b <- (RA|0)
 609     EA <- b + EXTS(D)
 610     r <- RT[0:63]
 611     do while r <=  31
 612         GPR(r) <- [0]*32 || MEM(EA, 4)
 613         r <- r + 1
 614         EA <- EA + 4
 615
 616 Special Registers Altered:
 617
 618     None
 619