1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
29 # Load Byte and Zero Shifted Indexed
38 EA <- b + (RB) << (SH+1)
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum of the contents of
44 register RB shifted by (SH+1), and (RA|0).
46 The byte in storage addressed by EA is loaded into RT[56:63].
47 RT[0:55] are set to 0.
49 Special Registers Altered:
53 # Load Byte and Zero Shifted with Update Indexed
61 EA <- (RA) + (RB) << (SH+1)
62 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
67 Let the effective address (EA) be the sum of the contents of
68 register RB shifted by (SH+1), and the contents of register RA.
70 The byte in storage addressed by EA is loaded into RT[56:63].
71 RT[0:55] are set to 0.
73 EA is placed into register RA.
75 If RA=0, the instruction form is invalid.
77 Special Registers Altered:
81 # Load Halfword and Zero Shifted Indexed
90 EA <- b + (RB) << (SH+1)
91 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
95 Let the effective address (EA) be the sum of the contents of
96 register RB shifted by (SH+1), and (RA|0).
98 The halfword in storage addressed by EA is loaded into RT[48:63].
99 RT[0:47] are set to 0.
101 Special Registers Altered:
105 # Load Halfword and Zero Shifted with Update Indexed
113 EA <- (RA) + (RB) << (SH+1)
114 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
119 Let the effective address (EA) be the sum of the contents of
120 register RB shifted by (SH+1), and the contents of register RA.
122 The halfword in storage addressed by EA is loaded into RT[48:63].
123 RT[0:47] are set to 0.
125 EA is placed into register RA.
127 If RA=0, the instruction form is invalid.
129 Special Registers Altered:
133 # Load Halfword Algebraic Shifted Indexed
142 EA <- b + (RB) << (SH+1)
143 RT <- EXTS(MEM(EA, 2))
147 Let the effective address (EA) be the sum of the contents of
148 register RB shifted by (SH+1), and (RA|0).
150 The halfword in storage addressed by EA is loaded into RT[48:63].
151 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
153 Special Registers Altered:
157 # Load Halfword Algebraic Shifted with Update Indexed
165 EA <- (RA) + (RB) << (SH+1)
166 RT <- EXTS(MEM(EA, 2))
171 Let the effective address (EA) be the sum of the contents of
172 register RB shifted by (SH+1), and the contents of register RA.
174 The halfword in storage addressed by EA is loaded into RT[48:63].
175 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
177 EA is placed into register RA.
179 If RA=0 or RA=RT, the instruction form is invalid.
181 Special Registers Altered:
185 # Load Word and Zero Shifted Indexed
194 EA <- b + (RB) << (SH+1)
195 RT <- [0] * 32 || MEM(EA, 4)
199 Let the effective address (EA) be the sum of the contents of
200 register RB shifted by (SH+1), and (RA|0).
202 The word in storage addressed by EA is loaded into RT[32:63].
203 RT[0:31] are set to 0.
205 Special Registers Altered:
209 # Load Word and Zero Shifted with Update Indexed
217 EA <- (RA) + (RB) << (SH+1)
218 RT <- [0] * 32 || MEM(EA, 4)
223 Let the effective address (EA) be the sum of the contents of
224 register RB shifted by (SH+1), and the contents of register RA.
226 The word in storage addressed by EA is loaded into RT[32:63].
227 RT[0:31] are set to 0.
229 EA is placed into register RA.
231 If RA=0 or RA=RT, the instruction form is invalid.
233 Special Registers Altered:
237 # Load Word Algebraic Shifted Indexed
246 EA <- b + (RB) << (SH+1)
247 RT <- EXTS(MEM(EA, 4))
251 Let the effective address (EA) be the sum of the contents of
252 register RB shifted by (SH+1), and (RA|0).
254 The word in storage addressed by EA is loaded into RT[32:63].
255 RT[0:31] are filled with a copy of bit 0 of the loaded word.
257 Special Registers Altered:
261 # Load Word Algebraic Shifted with Update Indexed
269 EA <- (RA) + (RB) << (SH+1)
270 RT <- EXTS(MEM(EA, 4))
275 Let the effective address (EA) be the sum of the contents of
276 register RB shifted by (SH+1), and the contents of register RA.
278 The word in storage addressed by EA is loaded into RT[32:63].
279 RT[0:31] are filled with a copy of bit 0 of the loaded word.
281 EA is placed into register RA.
283 If RA=0 or RA=RT, the instruction form is invalid.
285 Special Registers Altered:
289 # Load Doubleword Shifted Indexed
298 EA <- b + (RB) << (SH+1)
303 Let the effective address (EA) be the sum of the contents of
304 register RB shifted by (SH+1), and (RA|0).
306 The doubleword in storage addressed by EA is loaded into RT.
308 Special Registers Altered:
312 # Load Doubleword Shifted with Update Indexed
320 EA <- (RA) + (RB) << (SH+1)
326 Let the effective address (EA) be the sum of the contents of
327 register RB shifted by (SH+1), and (RA).
329 The doubleword in storage addressed by EA is loaded into RT.
331 EA is placed into register RA.
333 If RA=0 or RA=RT, the instruction form is invalid.
335 Special Registers Altered:
339 <!-- byte-reverse shifted -->
341 # Load Halfword Byte-Reverse Shifted Indexed
350 EA <- b + (RB) << (SH+1)
351 load_data <- MEM(EA, 2)
352 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
356 Let the effective address (EA) be the sum of the contents of
357 register RB shifted by (SH+1), and (RA|0).
359 Bits 0:7 of the halfword in storage addressed by EA are
360 loaded into RT[56:63]. Bits 8:15 of the halfword in storage
361 addressed by EA are loaded into RT[48:55].
362 RT[0:47] are set to 0.
365 Special Registers Altered:
369 # Load Word Byte-Reverse Shifted Indexed
378 EA <- b + (RB) << (SH+1)
379 load_data <- MEM(EA, 4)
380 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
381 || load_data[8:15] || load_data[0:7])
385 Let the effective address (EA) be the sum of the contents of
386 register RB shifted by (SH+1), and (RA|0).
388 Bits 0:7 of the word in storage addressed
389 by EA are loaded into RT[56:63]. Bits 8:15 of the word in
390 storage addressed by EA are loaded into RT[48:55]. Bits
391 16:23 of the word in storage addressed by EA are
392 loaded into RT[40:47]. Bits 24:31 of the word in storage
393 addressed by EA are loaded into RT 32:39.
394 RT[0:31] are set to 0.
396 Special Registers Altered:
401 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
403 # Load Doubleword Byte-Reverse Shifted Indexed
412 EA <- b + (RB) << (SH+1)
413 load_data <- MEM(EA, 8)
414 RT <- (load_data[56:63] || load_data[48:55]
415 || load_data[40:47] || load_data[32:39]
416 || load_data[24:31] || load_data[16:23]
417 || load_data[8:15] || load_data[0:7])
421 Let the effective address (EA) be the sum of the contents of
422 register RB shifted by (SH+1), and (RA|0).
424 Bits 0:7 of the doubleword in storage addressed by EA
425 are loaded into RT[56:63]. Bits 8:15 of the doubleword in
426 storage addressed by EA are loaded into RT[48:55]. Bits
427 16:23 of the doubleword in storage addressed by EA
428 are loaded into RT[40:47]. Bits 24:31 of the doubleword in
429 storage addressed by EA are loaded into RT 32:39. Bits
430 32:39 of the doubleword in storage addressed by EA
431 are loaded into RT[24:31]. Bits 40:47 of the doubleword in
432 storage addressed by EA are loaded into RT[16:23]. Bits
433 48:55 of the doubleword in storage addressed by EA
434 are loaded into RT[8:15]. Bits 56:63 of the doubleword in
435 storage addressed by EA are loaded into RT[0:7].
438 Special Registers Altered: