1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
29 # Load Byte and Zero Shifted Indexed
38 EA <- b + (RB) << (sm+1)
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
41 Special Registers Altered:
45 # Load Byte and Zero Shifted with Update Indexed
53 EA <- (RA) + (RB) << (sm+1)
54 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
57 Special Registers Altered:
61 # Load Halfword and Zero Shifted Indexed
70 EA <- b + (RB) << (sm+1)
71 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
73 Special Registers Altered:
77 # Load Halfword and Zero Shifted with Update Indexed
85 EA <- (RA) + (RB) << (sm+1)
86 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
89 Special Registers Altered:
93 # Load Halfword Algebraic Shifted Indexed
102 EA <- b + (RB) << (sm+1)
103 RT <- EXTS(MEM(EA, 2))
105 Special Registers Altered:
109 # Load Halfword Algebraic Shifted with Update Indexed
117 EA <- (RA) + (RB) << (sm+1)
118 RT <- EXTS(MEM(EA, 2))
121 Special Registers Altered:
125 # Load Word and Zero Shifted Indexed
134 EA <- b + (RB) << (sm+1)
135 RT <- [0] * 32 || MEM(EA, 4)
137 Special Registers Altered:
141 # Load Word and Zero Shifted with Update Indexed
149 EA <- (RA) + (RB) << (sm+1)
150 RT <- [0] * 32 || MEM(EA, 4)
153 Special Registers Altered:
157 # Load Word Algebraic Shifted Indexed
166 EA <- b + (RB) << (sm+1)
167 RT <- EXTS(MEM(EA, 4))
169 Special Registers Altered:
173 # Load Word Algebraic Shifted with Update Indexed
181 EA <- (RA) + (RB) << (sm+1)
182 RT <- EXTS(MEM(EA, 4))
185 Special Registers Altered:
189 # Load Doubleword Shifted Indexed
198 EA <- b + (RB) << (sm+1)
201 Special Registers Altered:
205 # Load Doubleword Shifted with Update Indexed
213 EA <- (RA) + (RB) << (sm+1)
217 Special Registers Altered:
221 <!-- byte-reverse shifted -->
223 # Load Halfword Byte-Reverse Shifted Indexed
232 EA <- b + (RB) << (sm+1)
233 load_data <- MEM(EA, 2)
234 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
236 Special Registers Altered:
240 # Load Word Byte-Reverse Shifted Indexed
249 EA <- b + (RB) << (sm+1)
250 load_data <- MEM(EA, 4)
251 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
252 || load_data[8:15] || load_data[0:7])
254 Special Registers Altered:
259 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
261 # Load Doubleword Byte-Reverse Shifted Indexed
270 EA <- b + (RB) << (sm+1)
271 load_data <- MEM(EA, 8)
272 RT <- (load_data[56:63] || load_data[48:55]
273 || load_data[40:47] || load_data[32:39]
274 || load_data[24:31] || load_data[16:23]
275 || load_data[8:15] || load_data[0:7])
277 Special Registers Altered: