openpower/isa/fixedloadshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero Shifted Indexed
  30
  31 X-Form
  32
  33 * lbzsx RT,RA,RB,SH
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + (RB) << (SH+1)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum of the contents of
  44     register RB shifted by (SH+1), and (RA|0).
  45
  46     The byte in storage addressed by EA is loaded into
  47     RT[56:63]. RT[0:55] are set to 0.
  48
  49
  50 Special Registers Altered:
  51
  52     None
  53
  54 # Load Byte and Zero Shifted with Update Indexed
  55
  56 X-Form
  57
  58 * lbzsux RT,RA,RB,SH
  59
  60 Pseudo-code:
  61
  62     EA <- (RA) + (RB) << (SH+1)
  63     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  64     RA <- EA
  65
  66 Description:
  67
  68     Let the effective address (EA) be the sum of the contents of
  69     register RB shifted by (SH+1), and (RA).
  70
  71     The byte in storage addressed by EA is
  72     loaded into RT[56:63] . RT[0:55] are set to 0.
  73
  74     EA is placed into register RA.
  75
  76     If RA=0, the instruction form is invalid.
  77
  78 Special Registers Altered:
  79
  80     None
  81
  82 # Load Halfword and Zero Shifted Indexed
  83
  84 X-Form
  85
  86 * lhzsx RT,RA,RB,SH
  87
  88 Pseudo-code:
  89
  90     b <- (RA|0)
  91     EA <- b + (RB) << (SH+1)
  92     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  93
  94 Description:
  95
  96     Let the effective address (EA) be the sum of the contents of
  97     register RB shifted by (SH+1), and (RA|0).
  98
  99     The halfword in storage addressed by EA is loaded into
 100     RT[48:63]. RT[0:47] are set to 0.
 101
 102
 103
 104 Special Registers Altered:
 105
 106     None
 107
 108 # Load Halfword and Zero Shifted with Update Indexed
 109
 110 X-Form
 111
 112 * lhzsux RT,RA,RB,SH
 113
 114 Pseudo-code:
 115
 116     EA <- (RA) + (RB) << (SH+1)
 117     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 118     RA <- EA
 119
 120 Special Registers Altered:
 121
 122     None
 123
 124 # Load Halfword Algebraic Shifted Indexed
 125
 126 X-Form
 127
 128 * lhasx RT,RA,RB,SH
 129
 130 Pseudo-code:
 131
 132     b <- (RA|0)
 133     EA <- b + (RB) << (SH+1)
 134     RT <- EXTS(MEM(EA, 2))
 135
 136 Special Registers Altered:
 137
 138     None
 139
 140 # Load Halfword Algebraic Shifted with Update Indexed
 141
 142 X-Form
 143
 144 * lhasux RT,RA,RB,SH
 145
 146 Pseudo-code:
 147
 148     EA <- (RA) + (RB) << (SH+1)
 149     RT <- EXTS(MEM(EA, 2))
 150     RA <- EA
 151
 152 Special Registers Altered:
 153
 154     None
 155
 156 # Load Word and Zero Shifted Indexed
 157
 158 X-Form
 159
 160 * lwzsx RT,RA,RB,SH
 161
 162 Pseudo-code:
 163
 164     b <- (RA|0)
 165     EA <- b + (RB) << (SH+1)
 166     RT <- [0] * 32 || MEM(EA, 4)
 167
 168 Special Registers Altered:
 169
 170     None
 171
 172 # Load Word and Zero Shifted with Update Indexed
 173
 174 X-Form
 175
 176 * lwzsux RT,RA,RB,SH
 177
 178 Pseudo-code:
 179
 180     EA <- (RA) + (RB) << (SH+1)
 181     RT <- [0] * 32 || MEM(EA, 4)
 182     RA <- EA
 183
 184 Special Registers Altered:
 185
 186     None
 187
 188 # Load Word Algebraic Shifted Indexed
 189
 190 X-Form
 191
 192 * lwasx RT,RA,RB,SH
 193
 194 Pseudo-code:
 195
 196     b <- (RA|0)
 197     EA <- b + (RB) << (SH+1)
 198     RT <- EXTS(MEM(EA, 4))
 199
 200 Special Registers Altered:
 201
 202     None
 203
 204 # Load Word Algebraic Shifted with Update Indexed
 205
 206 X-Form
 207
 208 * lwasux RT,RA,RB,SH
 209
 210 Pseudo-code:
 211
 212     EA <- (RA) + (RB) << (SH+1)
 213     RT <- EXTS(MEM(EA, 4))
 214     RA <- EA
 215
 216 Special Registers Altered:
 217
 218     None
 219
 220 # Load Doubleword Shifted Indexed
 221
 222 X-Form
 223
 224 * ldsx RT,RA,RB,SH
 225
 226 Pseudo-code:
 227
 228     b <- (RA|0)
 229     EA <- b + (RB) << (SH+1)
 230     RT <- MEM(EA, 8)
 231
 232 Special Registers Altered:
 233
 234     None
 235
 236 # Load Doubleword Shifted with Update Indexed
 237
 238 X-Form
 239
 240 * ldsux RT,RA,RB,SH
 241
 242 Pseudo-code:
 243
 244     EA <- (RA) + (RB) << (SH+1)
 245     RT <- MEM(EA, 8)
 246     RA <- EA
 247
 248 Special Registers Altered:
 249
 250     None
 251
 252 <!-- byte-reverse shifted -->
 253
 254 # Load Halfword Byte-Reverse Shifted Indexed
 255
 256 X-Form
 257
 258 * lhbrsx RT,RA,RB,SH
 259
 260 Pseudo-code:
 261
 262     b <- (RA|0)
 263     EA <- b + (RB) << (SH+1)
 264     load_data <- MEM(EA, 2)
 265     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 266
 267 Special Registers Altered:
 268
 269     None
 270
 271 # Load Word Byte-Reverse Shifted Indexed
 272
 273 X-Form
 274
 275 * lwbrsx RT,RA,RB,SH
 276
 277 Pseudo-code:
 278
 279     b <- (RA|0)
 280     EA <- b + (RB) << (SH+1)
 281     load_data <- MEM(EA, 4)
 282     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 283                     || load_data[8:15]  || load_data[0:7])
 284
 285 Special Registers Altered:
 286
 287     None
 288
 289
 290 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 291
 292 # Load Doubleword Byte-Reverse Shifted Indexed
 293
 294 X-Form
 295
 296 * ldbrsx RT,RA,RB,SH
 297
 298 Pseudo-code:
 299
 300     b <- (RA|0)
 301     EA <- b + (RB) << (SH+1)
 302     load_data <- MEM(EA, 8)
 303     RT <- (load_data[56:63] || load_data[48:55]
 304         || load_data[40:47] || load_data[32:39]
 305         || load_data[24:31] || load_data[16:23]
 306         || load_data[8:15]  || load_data[0:7])
 307
 308 Special Registers Altered:
 309
 310     None
 311