openpower/isa/fixedloadshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero Shifted Indexed
  30
  31 X-Form
  32
  33 * lbzsx RT,RA,RB,SH
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + (RB) << (SH+1)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum of the contents of
  44     register RB shifted by (SH+1), and (RA|0).
  45     The byte in storage addressed by EA is loaded into
  46     RT[56:63]. RT[0:55] are set to 0.
  47
  48
  49 Special Registers Altered:
  50
  51     None
  52
  53 # Load Byte and Zero Shifted with Update Indexed
  54
  55 X-Form
  56
  57 * lbzsux RT,RA,RB,SH
  58
  59 Pseudo-code:
  60
  61     EA <- (RA) + (RB) << (SH+1)
  62     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  63     RA <- EA
  64
  65 Special Registers Altered:
  66
  67     None
  68
  69 # Load Halfword and Zero Shifted Indexed
  70
  71 X-Form
  72
  73 * lhzsx RT,RA,RB,SH
  74
  75 Pseudo-code:
  76
  77     b <- (RA|0)
  78     EA <- b + (RB) << (SH+1)
  79     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  80
  81 Special Registers Altered:
  82
  83     None
  84
  85 # Load Halfword and Zero Shifted with Update Indexed
  86
  87 X-Form
  88
  89 * lhzsux RT,RA,RB,SH
  90
  91 Pseudo-code:
  92
  93     EA <- (RA) + (RB) << (SH+1)
  94     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  95     RA <- EA
  96
  97 Special Registers Altered:
  98
  99     None
 100
 101 # Load Halfword Algebraic Shifted Indexed
 102
 103 X-Form
 104
 105 * lhasx RT,RA,RB,SH
 106
 107 Pseudo-code:
 108
 109     b <- (RA|0)
 110     EA <- b + (RB) << (SH+1)
 111     RT <- EXTS(MEM(EA, 2))
 112
 113 Special Registers Altered:
 114
 115     None
 116
 117 # Load Halfword Algebraic Shifted with Update Indexed
 118
 119 X-Form
 120
 121 * lhasux RT,RA,RB,SH
 122
 123 Pseudo-code:
 124
 125     EA <- (RA) + (RB) << (SH+1)
 126     RT <- EXTS(MEM(EA, 2))
 127     RA <- EA
 128
 129 Special Registers Altered:
 130
 131     None
 132
 133 # Load Word and Zero Shifted Indexed
 134
 135 X-Form
 136
 137 * lwzsx RT,RA,RB,SH
 138
 139 Pseudo-code:
 140
 141     b <- (RA|0)
 142     EA <- b + (RB) << (SH+1)
 143     RT <- [0] * 32 || MEM(EA, 4)
 144
 145 Special Registers Altered:
 146
 147     None
 148
 149 # Load Word and Zero Shifted with Update Indexed
 150
 151 X-Form
 152
 153 * lwzsux RT,RA,RB,SH
 154
 155 Pseudo-code:
 156
 157     EA <- (RA) + (RB) << (SH+1)
 158     RT <- [0] * 32 || MEM(EA, 4)
 159     RA <- EA
 160
 161 Special Registers Altered:
 162
 163     None
 164
 165 # Load Word Algebraic Shifted Indexed
 166
 167 X-Form
 168
 169 * lwasx RT,RA,RB,SH
 170
 171 Pseudo-code:
 172
 173     b <- (RA|0)
 174     EA <- b + (RB) << (SH+1)
 175     RT <- EXTS(MEM(EA, 4))
 176
 177 Special Registers Altered:
 178
 179     None
 180
 181 # Load Word Algebraic Shifted with Update Indexed
 182
 183 X-Form
 184
 185 * lwasux RT,RA,RB,SH
 186
 187 Pseudo-code:
 188
 189     EA <- (RA) + (RB) << (SH+1)
 190     RT <- EXTS(MEM(EA, 4))
 191     RA <- EA
 192
 193 Special Registers Altered:
 194
 195     None
 196
 197 # Load Doubleword Shifted Indexed
 198
 199 X-Form
 200
 201 * ldsx RT,RA,RB,SH
 202
 203 Pseudo-code:
 204
 205     b <- (RA|0)
 206     EA <- b + (RB) << (SH+1)
 207     RT <- MEM(EA, 8)
 208
 209 Special Registers Altered:
 210
 211     None
 212
 213 # Load Doubleword Shifted with Update Indexed
 214
 215 X-Form
 216
 217 * ldsux RT,RA,RB,SH
 218
 219 Pseudo-code:
 220
 221     EA <- (RA) + (RB) << (SH+1)
 222     RT <- MEM(EA, 8)
 223     RA <- EA
 224
 225 Special Registers Altered:
 226
 227     None
 228
 229 <!-- byte-reverse shifted -->
 230
 231 # Load Halfword Byte-Reverse Shifted Indexed
 232
 233 X-Form
 234
 235 * lhbrsx RT,RA,RB,SH
 236
 237 Pseudo-code:
 238
 239     b <- (RA|0)
 240     EA <- b + (RB) << (SH+1)
 241     load_data <- MEM(EA, 2)
 242     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 243
 244 Special Registers Altered:
 245
 246     None
 247
 248 # Load Word Byte-Reverse Shifted Indexed
 249
 250 X-Form
 251
 252 * lwbrsx RT,RA,RB,SH
 253
 254 Pseudo-code:
 255
 256     b <- (RA|0)
 257     EA <- b + (RB) << (SH+1)
 258     load_data <- MEM(EA, 4)
 259     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 260                     || load_data[8:15]  || load_data[0:7])
 261
 262 Special Registers Altered:
 263
 264     None
 265
 266
 267 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 268
 269 # Load Doubleword Byte-Reverse Shifted Indexed
 270
 271 X-Form
 272
 273 * ldbrsx RT,RA,RB,SH
 274
 275 Pseudo-code:
 276
 277     b <- (RA|0)
 278     EA <- b + (RB) << (SH+1)
 279     load_data <- MEM(EA, 8)
 280     RT <- (load_data[56:63] || load_data[48:55]
 281         || load_data[40:47] || load_data[32:39]
 282         || load_data[24:31] || load_data[16:23]
 283         || load_data[8:15]  || load_data[0:7])
 284
 285 Special Registers Altered:
 286
 287     None
 288