1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that load from RAM to a register -->
5 <!-- Note that these pages also define equivalent store instructions, -->
6 <!-- these are described in fixedstore.mdwn -->
8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
21 <!-- into register RT. -->
23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
25 <!-- effective address is placed into register RA and the storage element (byte, -->
26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
29 # Load Byte and Zero Shifted Indexed
38 EA <- b + (RB) << (SH+1)
39 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
43 Let the effective address (EA) be the sum of the contents of
44 register RB shifted by (SH+1), and (RA|0).
46 The byte in storage addressed by EA is loaded into RT[56:63].
47 RT[0:55] are set to 0.
49 Special Registers Altered:
53 # Load Byte and Zero Shifted with Update Indexed
61 EA <- (RA) + (RB) << (SH+1)
62 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
67 Let the effective address (EA) be the sum of the contents of
68 register RB shifted by (SH+1), and the contents of register RA.
70 The byte in storage addressed by EA is loaded into RT[56:63].
71 RT[0:55] are set to 0.
73 EA is placed into register RA.
75 If RA=0, the instruction form is invalid.
77 Special Registers Altered:
81 # Load Halfword and Zero Shifted Indexed
90 EA <- b + (RB) << (SH+1)
91 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
95 Let the effective address (EA) be the sum of the contents of
96 register RB shifted by (SH+1), and (RA|0).
98 The halfword in storage addressed by EA is loaded into
99 RT[48:63]. RT[0:47] are set to 0.
101 Special Registers Altered:
105 # Load Halfword and Zero Shifted with Update Indexed
113 EA <- (RA) + (RB) << (SH+1)
114 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
119 Let the effective address (EA) be the sum of the contents of
120 register RB shifted by (SH+1), and (RA).
122 The halfword in storage addressed by EA is loaded into RT[48:63].
123 RT[0:47] are set to 0.
125 EA is placed into register RA.
127 If RA=0, the instruction form is invalid.
129 Special Registers Altered:
133 # Load Halfword Algebraic Shifted Indexed
142 EA <- b + (RB) << (SH+1)
143 RT <- EXTS(MEM(EA, 2))
147 Let the effective address (EA) be the sum of the contents of
148 register RB shifted by (SH+1), and (RA|0).
150 The halfword in storage addressed by EA is loaded into RT[48:63].
151 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
153 Special Registers Altered:
157 # Load Halfword Algebraic Shifted with Update Indexed
165 EA <- (RA) + (RB) << (SH+1)
166 RT <- EXTS(MEM(EA, 2))
171 Let the effective address (EA) be the sum of the contents of
172 register (RB) shifted by (SH+1), and (RA).
174 The halfword in storage addressed by EA is loaded into RT[48:63].
175 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
177 EA is placed into register RA.
179 If RA=0 or RA=RT, the instruction form is invalid.
181 Special Registers Altered:
185 # Load Word and Zero Shifted Indexed
194 EA <- b + (RB) << (SH+1)
195 RT <- [0] * 32 || MEM(EA, 4)
197 Special Registers Altered:
201 # Load Word and Zero Shifted with Update Indexed
209 EA <- (RA) + (RB) << (SH+1)
210 RT <- [0] * 32 || MEM(EA, 4)
213 Special Registers Altered:
217 # Load Word Algebraic Shifted Indexed
226 EA <- b + (RB) << (SH+1)
227 RT <- EXTS(MEM(EA, 4))
229 Special Registers Altered:
233 # Load Word Algebraic Shifted with Update Indexed
241 EA <- (RA) + (RB) << (SH+1)
242 RT <- EXTS(MEM(EA, 4))
245 Special Registers Altered:
249 # Load Doubleword Shifted Indexed
258 EA <- b + (RB) << (SH+1)
261 Special Registers Altered:
265 # Load Doubleword Shifted with Update Indexed
273 EA <- (RA) + (RB) << (SH+1)
277 Special Registers Altered:
281 <!-- byte-reverse shifted -->
283 # Load Halfword Byte-Reverse Shifted Indexed
292 EA <- b + (RB) << (SH+1)
293 load_data <- MEM(EA, 2)
294 RT <- [0]*48 || load_data[8:15] || load_data[0:7]
296 Special Registers Altered:
300 # Load Word Byte-Reverse Shifted Indexed
309 EA <- b + (RB) << (SH+1)
310 load_data <- MEM(EA, 4)
311 RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
312 || load_data[8:15] || load_data[0:7])
314 Special Registers Altered:
319 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
321 # Load Doubleword Byte-Reverse Shifted Indexed
330 EA <- b + (RB) << (SH+1)
331 load_data <- MEM(EA, 8)
332 RT <- (load_data[56:63] || load_data[48:55]
333 || load_data[40:47] || load_data[32:39]
334 || load_data[24:31] || load_data[16:23]
335 || load_data[8:15] || load_data[0:7])
337 Special Registers Altered: