openpower/isa/fixedloadshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero Shifted Indexed
  30
  31 X-Form
  32
  33 * lbzsx RT,RA,RB,SH
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + (RB) << (SH+1)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum of the contents of
  44     register RB shifted by (SH+1), and (RA|0).
  45
  46     The byte in storage addressed by EA is loaded into
  47     RT[56:63]. RT[0:55] are set to 0.
  48
  49
  50 Special Registers Altered:
  51
  52     None
  53
  54 # Load Byte and Zero Shifted with Update Indexed
  55
  56 X-Form
  57
  58 * lbzsux RT,RA,RB,SH
  59
  60 Pseudo-code:
  61
  62     EA <- (RA) + (RB) << (SH+1)
  63     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  64     RA <- EA
  65
  66 Description:
  67
  68     Let the effective address (EA) be the sum of the contents of
  69     register RB shifted by (SH+1), and (RA).
  70
  71     The byte in storage addressed by EA is
  72     loaded into RT[56:63] . RT[0:55] are set to 0.
  73
  74     EA is placed into register RA.
  75
  76     If RA=0, the instruction form is invalid.
  77
  78 Special Registers Altered:
  79
  80     None
  81
  82 # Load Halfword and Zero Shifted Indexed
  83
  84 X-Form
  85
  86 * lhzsx RT,RA,RB,SH
  87
  88 Pseudo-code:
  89
  90     b <- (RA|0)
  91     EA <- b + (RB) << (SH+1)
  92     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  93
  94 Description:
  95
  96     Let the effective address (EA) be the sum of the contents of
  97     register RB shifted by (SH+1), and (RA|0).
  98
  99     The halfword in storage addressed by EA is loaded into
 100     RT[48:63]. RT[0:47] are set to 0.
 101
 102 Special Registers Altered:
 103
 104     None
 105
 106 # Load Halfword and Zero Shifted with Update Indexed
 107
 108 X-Form
 109
 110 * lhzsux RT,RA,RB,SH
 111
 112 Pseudo-code:
 113
 114     EA <- (RA) + (RB) << (SH+1)
 115     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 116     RA <- EA
 117
 118 Description:
 119
 120     Let the effective address (EA) be the sum of the contents of
 121     register RB shifted by (SH+1), and (RA).
 122
 123     The halfword in storage addressed by EA is loaded into RT[48:63].
 124     RT[0:47] are set to 0.
 125
 126     EA is placed into register RA.
 127
 128     If RA=0, the instruction form is invalid.
 129
 130 Special Registers Altered:
 131
 132     None
 133
 134 # Load Halfword Algebraic Shifted Indexed
 135
 136 X-Form
 137
 138 * lhasx RT,RA,RB,SH
 139
 140 Pseudo-code:
 141
 142     b <- (RA|0)
 143     EA <- b + (RB) << (SH+1)
 144     RT <- EXTS(MEM(EA, 2))
 145
 146 Description:
 147
 148     Let the effective address (EA) be the sum of the contents of
 149     register RB shifted by (SH+1), and (RA|0).
 150
 151     The halfword in storage addressed by EA is loaded into RT[48:63].
 152     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 153
 154 Special Registers Altered:
 155
 156     None
 157
 158 # Load Halfword Algebraic Shifted with Update Indexed
 159
 160 X-Form
 161
 162 * lhasux RT,RA,RB,SH
 163
 164 Pseudo-code:
 165
 166     EA <- (RA) + (RB) << (SH+1)
 167     RT <- EXTS(MEM(EA, 2))
 168     RA <- EA
 169
 170 Special Registers Altered:
 171
 172     None
 173
 174 # Load Word and Zero Shifted Indexed
 175
 176 X-Form
 177
 178 * lwzsx RT,RA,RB,SH
 179
 180 Pseudo-code:
 181
 182     b <- (RA|0)
 183     EA <- b + (RB) << (SH+1)
 184     RT <- [0] * 32 || MEM(EA, 4)
 185
 186 Special Registers Altered:
 187
 188     None
 189
 190 # Load Word and Zero Shifted with Update Indexed
 191
 192 X-Form
 193
 194 * lwzsux RT,RA,RB,SH
 195
 196 Pseudo-code:
 197
 198     EA <- (RA) + (RB) << (SH+1)
 199     RT <- [0] * 32 || MEM(EA, 4)
 200     RA <- EA
 201
 202 Special Registers Altered:
 203
 204     None
 205
 206 # Load Word Algebraic Shifted Indexed
 207
 208 X-Form
 209
 210 * lwasx RT,RA,RB,SH
 211
 212 Pseudo-code:
 213
 214     b <- (RA|0)
 215     EA <- b + (RB) << (SH+1)
 216     RT <- EXTS(MEM(EA, 4))
 217
 218 Special Registers Altered:
 219
 220     None
 221
 222 # Load Word Algebraic Shifted with Update Indexed
 223
 224 X-Form
 225
 226 * lwasux RT,RA,RB,SH
 227
 228 Pseudo-code:
 229
 230     EA <- (RA) + (RB) << (SH+1)
 231     RT <- EXTS(MEM(EA, 4))
 232     RA <- EA
 233
 234 Special Registers Altered:
 235
 236     None
 237
 238 # Load Doubleword Shifted Indexed
 239
 240 X-Form
 241
 242 * ldsx RT,RA,RB,SH
 243
 244 Pseudo-code:
 245
 246     b <- (RA|0)
 247     EA <- b + (RB) << (SH+1)
 248     RT <- MEM(EA, 8)
 249
 250 Special Registers Altered:
 251
 252     None
 253
 254 # Load Doubleword Shifted with Update Indexed
 255
 256 X-Form
 257
 258 * ldsux RT,RA,RB,SH
 259
 260 Pseudo-code:
 261
 262     EA <- (RA) + (RB) << (SH+1)
 263     RT <- MEM(EA, 8)
 264     RA <- EA
 265
 266 Special Registers Altered:
 267
 268     None
 269
 270 <!-- byte-reverse shifted -->
 271
 272 # Load Halfword Byte-Reverse Shifted Indexed
 273
 274 X-Form
 275
 276 * lhbrsx RT,RA,RB,SH
 277
 278 Pseudo-code:
 279
 280     b <- (RA|0)
 281     EA <- b + (RB) << (SH+1)
 282     load_data <- MEM(EA, 2)
 283     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 284
 285 Special Registers Altered:
 286
 287     None
 288
 289 # Load Word Byte-Reverse Shifted Indexed
 290
 291 X-Form
 292
 293 * lwbrsx RT,RA,RB,SH
 294
 295 Pseudo-code:
 296
 297     b <- (RA|0)
 298     EA <- b + (RB) << (SH+1)
 299     load_data <- MEM(EA, 4)
 300     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 301                     || load_data[8:15]  || load_data[0:7])
 302
 303 Special Registers Altered:
 304
 305     None
 306
 307
 308 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 309
 310 # Load Doubleword Byte-Reverse Shifted Indexed
 311
 312 X-Form
 313
 314 * ldbrsx RT,RA,RB,SH
 315
 316 Pseudo-code:
 317
 318     b <- (RA|0)
 319     EA <- b + (RB) << (SH+1)
 320     load_data <- MEM(EA, 8)
 321     RT <- (load_data[56:63] || load_data[48:55]
 322         || load_data[40:47] || load_data[32:39]
 323         || load_data[24:31] || load_data[16:23]
 324         || load_data[8:15]  || load_data[0:7])
 325
 326 Special Registers Altered:
 327
 328     None
 329