openpower/isa/fixedloadshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero Shifted Indexed
  30
  31 X-Form
  32
  33 * lbzsx RT,RA,RB,SH
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + (RB) << (SH+1)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum of the contents of
  44     register RB shifted by (SH+1), and (RA|0).
  45
  46     The byte in storage addressed by EA is loaded into RT[56:63].
  47     RT[0:55] are set to 0.
  48
  49 Special Registers Altered:
  50
  51     None
  52
  53 # Load Byte and Zero Shifted with Update Indexed
  54
  55 X-Form
  56
  57 * lbzsux RT,RA,RB,SH
  58
  59 Pseudo-code:
  60
  61     EA <- (RA) + (RB) << (SH+1)
  62     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  63     RA <- EA
  64
  65 Description:
  66
  67     Let the effective address (EA) be the sum of the contents of
  68     register RB shifted by (SH+1), and (RA).
  69
  70     The byte in storage addressed by EA is
  71     loaded into RT[56:63] . RT[0:55] are set to 0.
  72
  73     EA is placed into register RA.
  74
  75     If RA=0, the instruction form is invalid.
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Load Halfword and Zero Shifted Indexed
  82
  83 X-Form
  84
  85 * lhzsx RT,RA,RB,SH
  86
  87 Pseudo-code:
  88
  89     b <- (RA|0)
  90     EA <- b + (RB) << (SH+1)
  91     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  92
  93 Description:
  94
  95     Let the effective address (EA) be the sum of the contents of
  96     register RB shifted by (SH+1), and (RA|0).
  97
  98     The halfword in storage addressed by EA is loaded into
  99     RT[48:63]. RT[0:47] are set to 0.
 100
 101 Special Registers Altered:
 102
 103     None
 104
 105 # Load Halfword and Zero Shifted with Update Indexed
 106
 107 X-Form
 108
 109 * lhzsux RT,RA,RB,SH
 110
 111 Pseudo-code:
 112
 113     EA <- (RA) + (RB) << (SH+1)
 114     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 115     RA <- EA
 116
 117 Description:
 118
 119     Let the effective address (EA) be the sum of the contents of
 120     register RB shifted by (SH+1), and (RA).
 121
 122     The halfword in storage addressed by EA is loaded into RT[48:63].
 123     RT[0:47] are set to 0.
 124
 125     EA is placed into register RA.
 126
 127     If RA=0, the instruction form is invalid.
 128
 129 Special Registers Altered:
 130
 131     None
 132
 133 # Load Halfword Algebraic Shifted Indexed
 134
 135 X-Form
 136
 137 * lhasx RT,RA,RB,SH
 138
 139 Pseudo-code:
 140
 141     b <- (RA|0)
 142     EA <- b + (RB) << (SH+1)
 143     RT <- EXTS(MEM(EA, 2))
 144
 145 Description:
 146
 147     Let the effective address (EA) be the sum of the contents of
 148     register RB shifted by (SH+1), and (RA|0).
 149
 150     The halfword in storage addressed by EA is loaded into RT[48:63].
 151     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Load Halfword Algebraic Shifted with Update Indexed
 158
 159 X-Form
 160
 161 * lhasux RT,RA,RB,SH
 162
 163 Pseudo-code:
 164
 165     EA <- (RA) + (RB) << (SH+1)
 166     RT <- EXTS(MEM(EA, 2))
 167     RA <- EA
 168
 169 Special Registers Altered:
 170
 171     None
 172
 173 # Load Word and Zero Shifted Indexed
 174
 175 X-Form
 176
 177 * lwzsx RT,RA,RB,SH
 178
 179 Pseudo-code:
 180
 181     b <- (RA|0)
 182     EA <- b + (RB) << (SH+1)
 183     RT <- [0] * 32 || MEM(EA, 4)
 184
 185 Special Registers Altered:
 186
 187     None
 188
 189 # Load Word and Zero Shifted with Update Indexed
 190
 191 X-Form
 192
 193 * lwzsux RT,RA,RB,SH
 194
 195 Pseudo-code:
 196
 197     EA <- (RA) + (RB) << (SH+1)
 198     RT <- [0] * 32 || MEM(EA, 4)
 199     RA <- EA
 200
 201 Special Registers Altered:
 202
 203     None
 204
 205 # Load Word Algebraic Shifted Indexed
 206
 207 X-Form
 208
 209 * lwasx RT,RA,RB,SH
 210
 211 Pseudo-code:
 212
 213     b <- (RA|0)
 214     EA <- b + (RB) << (SH+1)
 215     RT <- EXTS(MEM(EA, 4))
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221 # Load Word Algebraic Shifted with Update Indexed
 222
 223 X-Form
 224
 225 * lwasux RT,RA,RB,SH
 226
 227 Pseudo-code:
 228
 229     EA <- (RA) + (RB) << (SH+1)
 230     RT <- EXTS(MEM(EA, 4))
 231     RA <- EA
 232
 233 Special Registers Altered:
 234
 235     None
 236
 237 # Load Doubleword Shifted Indexed
 238
 239 X-Form
 240
 241 * ldsx RT,RA,RB,SH
 242
 243 Pseudo-code:
 244
 245     b <- (RA|0)
 246     EA <- b + (RB) << (SH+1)
 247     RT <- MEM(EA, 8)
 248
 249 Special Registers Altered:
 250
 251     None
 252
 253 # Load Doubleword Shifted with Update Indexed
 254
 255 X-Form
 256
 257 * ldsux RT,RA,RB,SH
 258
 259 Pseudo-code:
 260
 261     EA <- (RA) + (RB) << (SH+1)
 262     RT <- MEM(EA, 8)
 263     RA <- EA
 264
 265 Special Registers Altered:
 266
 267     None
 268
 269 <!-- byte-reverse shifted -->
 270
 271 # Load Halfword Byte-Reverse Shifted Indexed
 272
 273 X-Form
 274
 275 * lhbrsx RT,RA,RB,SH
 276
 277 Pseudo-code:
 278
 279     b <- (RA|0)
 280     EA <- b + (RB) << (SH+1)
 281     load_data <- MEM(EA, 2)
 282     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 283
 284 Special Registers Altered:
 285
 286     None
 287
 288 # Load Word Byte-Reverse Shifted Indexed
 289
 290 X-Form
 291
 292 * lwbrsx RT,RA,RB,SH
 293
 294 Pseudo-code:
 295
 296     b <- (RA|0)
 297     EA <- b + (RB) << (SH+1)
 298     load_data <- MEM(EA, 4)
 299     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 300                     || load_data[8:15]  || load_data[0:7])
 301
 302 Special Registers Altered:
 303
 304     None
 305
 306
 307 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 308
 309 # Load Doubleword Byte-Reverse Shifted Indexed
 310
 311 X-Form
 312
 313 * ldbrsx RT,RA,RB,SH
 314
 315 Pseudo-code:
 316
 317     b <- (RA|0)
 318     EA <- b + (RB) << (SH+1)
 319     load_data <- MEM(EA, 8)
 320     RT <- (load_data[56:63] || load_data[48:55]
 321         || load_data[40:47] || load_data[32:39]
 322         || load_data[24:31] || load_data[16:23]
 323         || load_data[8:15]  || load_data[0:7])
 324
 325 Special Registers Altered:
 326
 327     None
 328