openpower/isa/fixedloadshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero Shifted Indexed
  30
  31 X-Form
  32
  33 * lbzsx RT,RA,RB,SH
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + (RB) << (SH+1)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum of the contents of
  44     register RB shifted by (SH+1), and (RA|0).
  45
  46     The byte in storage addressed by EA is loaded into RT[56:63].
  47     RT[0:55] are set to 0.
  48
  49 Special Registers Altered:
  50
  51     None
  52
  53 # Load Byte and Zero Shifted with Update Indexed
  54
  55 X-Form
  56
  57 * lbzsux RT,RA,RB,SH
  58
  59 Pseudo-code:
  60
  61     EA <- (RA) + (RB) << (SH+1)
  62     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  63     RA <- EA
  64
  65 Description:
  66
  67     Let the effective address (EA) be the sum of the contents of
  68     register RB shifted by (SH+1), and the contents of register RA.
  69
  70     The byte in storage addressed by EA is loaded into RT[56:63].
  71     RT[0:55] are set to 0.
  72
  73     EA is placed into register RA.
  74
  75     If RA=0, the instruction form is invalid.
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Load Halfword and Zero Shifted Indexed
  82
  83 X-Form
  84
  85 * lhzsx RT,RA,RB,SH
  86
  87 Pseudo-code:
  88
  89     b <- (RA|0)
  90     EA <- b + (RB) << (SH+1)
  91     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  92
  93 Description:
  94
  95     Let the effective address (EA) be the sum of the contents of
  96     register RB shifted by (SH+1), and (RA|0).
  97
  98     The halfword in storage addressed by EA is loaded into RT[48:63].
  99     RT[0:47] are set to 0.
 100
 101 Special Registers Altered:
 102
 103     None
 104
 105 # Load Halfword and Zero Shifted with Update Indexed
 106
 107 X-Form
 108
 109 * lhzsux RT,RA,RB,SH
 110
 111 Pseudo-code:
 112
 113     EA <- (RA) + (RB) << (SH+1)
 114     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 115     RA <- EA
 116
 117 Description:
 118
 119     Let the effective address (EA) be the sum of the contents of
 120     register RB shifted by (SH+1), and (RA).
 121
 122     The halfword in storage addressed by EA is loaded into RT[48:63].
 123     RT[0:47] are set to 0.
 124
 125     EA is placed into register RA.
 126
 127     If RA=0, the instruction form is invalid.
 128
 129 Special Registers Altered:
 130
 131     None
 132
 133 # Load Halfword Algebraic Shifted Indexed
 134
 135 X-Form
 136
 137 * lhasx RT,RA,RB,SH
 138
 139 Pseudo-code:
 140
 141     b <- (RA|0)
 142     EA <- b + (RB) << (SH+1)
 143     RT <- EXTS(MEM(EA, 2))
 144
 145 Description:
 146
 147     Let the effective address (EA) be the sum of the contents of
 148     register RB shifted by (SH+1), and (RA|0).
 149
 150     The halfword in storage addressed by EA is loaded into RT[48:63].
 151     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Load Halfword Algebraic Shifted with Update Indexed
 158
 159 X-Form
 160
 161 * lhasux RT,RA,RB,SH
 162
 163 Pseudo-code:
 164
 165     EA <- (RA) + (RB) << (SH+1)
 166     RT <- EXTS(MEM(EA, 2))
 167     RA <- EA
 168
 169 Description:
 170
 171     Let the effective address (EA) be the sum of the contents of
 172     register (RB) shifted by (SH+1), and (RA).
 173
 174     The halfword in storage addressed by EA is loaded into RT[48:63].
 175     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 176
 177     EA is placed into register RA.
 178
 179     If RA=0 or RA=RT, the instruction form is invalid.
 180
 181 Special Registers Altered:
 182
 183     None
 184
 185 # Load Word and Zero Shifted Indexed
 186
 187 X-Form
 188
 189 * lwzsx RT,RA,RB,SH
 190
 191 Pseudo-code:
 192
 193     b <- (RA|0)
 194     EA <- b + (RB) << (SH+1)
 195     RT <- [0] * 32 || MEM(EA, 4)
 196
 197 Special Registers Altered:
 198
 199     None
 200
 201 # Load Word and Zero Shifted with Update Indexed
 202
 203 X-Form
 204
 205 * lwzsux RT,RA,RB,SH
 206
 207 Pseudo-code:
 208
 209     EA <- (RA) + (RB) << (SH+1)
 210     RT <- [0] * 32 || MEM(EA, 4)
 211     RA <- EA
 212
 213 Special Registers Altered:
 214
 215     None
 216
 217 # Load Word Algebraic Shifted Indexed
 218
 219 X-Form
 220
 221 * lwasx RT,RA,RB,SH
 222
 223 Pseudo-code:
 224
 225     b <- (RA|0)
 226     EA <- b + (RB) << (SH+1)
 227     RT <- EXTS(MEM(EA, 4))
 228
 229 Special Registers Altered:
 230
 231     None
 232
 233 # Load Word Algebraic Shifted with Update Indexed
 234
 235 X-Form
 236
 237 * lwasux RT,RA,RB,SH
 238
 239 Pseudo-code:
 240
 241     EA <- (RA) + (RB) << (SH+1)
 242     RT <- EXTS(MEM(EA, 4))
 243     RA <- EA
 244
 245 Special Registers Altered:
 246
 247     None
 248
 249 # Load Doubleword Shifted Indexed
 250
 251 X-Form
 252
 253 * ldsx RT,RA,RB,SH
 254
 255 Pseudo-code:
 256
 257     b <- (RA|0)
 258     EA <- b + (RB) << (SH+1)
 259     RT <- MEM(EA, 8)
 260
 261 Special Registers Altered:
 262
 263     None
 264
 265 # Load Doubleword Shifted with Update Indexed
 266
 267 X-Form
 268
 269 * ldsux RT,RA,RB,SH
 270
 271 Pseudo-code:
 272
 273     EA <- (RA) + (RB) << (SH+1)
 274     RT <- MEM(EA, 8)
 275     RA <- EA
 276
 277 Special Registers Altered:
 278
 279     None
 280
 281 <!-- byte-reverse shifted -->
 282
 283 # Load Halfword Byte-Reverse Shifted Indexed
 284
 285 X-Form
 286
 287 * lhbrsx RT,RA,RB,SH
 288
 289 Pseudo-code:
 290
 291     b <- (RA|0)
 292     EA <- b + (RB) << (SH+1)
 293     load_data <- MEM(EA, 2)
 294     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 295
 296 Special Registers Altered:
 297
 298     None
 299
 300 # Load Word Byte-Reverse Shifted Indexed
 301
 302 X-Form
 303
 304 * lwbrsx RT,RA,RB,SH
 305
 306 Pseudo-code:
 307
 308     b <- (RA|0)
 309     EA <- b + (RB) << (SH+1)
 310     load_data <- MEM(EA, 4)
 311     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 312                     || load_data[8:15]  || load_data[0:7])
 313
 314 Special Registers Altered:
 315
 316     None
 317
 318
 319 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 320
 321 # Load Doubleword Byte-Reverse Shifted Indexed
 322
 323 X-Form
 324
 325 * ldbrsx RT,RA,RB,SH
 326
 327 Pseudo-code:
 328
 329     b <- (RA|0)
 330     EA <- b + (RB) << (SH+1)
 331     load_data <- MEM(EA, 8)
 332     RT <- (load_data[56:63] || load_data[48:55]
 333         || load_data[40:47] || load_data[32:39]
 334         || load_data[24:31] || load_data[16:23]
 335         || load_data[8:15]  || load_data[0:7])
 336
 337 Special Registers Altered:
 338
 339     None
 340