openpower/isa/fixedloadshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4
   5 <!-- Note that these pages also define equivalent store instructions, -->
   6 <!-- these are described in fixedstore.mdwn -->
   7
   8 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
   9 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 56 -->
  10 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions pages 57 -->
  11 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  12 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  13 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  14 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  15
  16
  17
  18 <!-- Section 3.3.2 This defines the Fixed-Point Load Instructions pages 47 - 53 -->
  19
  20 <!-- The byte, halfword, word, or doubleword in storage addressed by EA is loaded -->
  21 <!-- into register RT. -->
  22
  23 <!-- Many of the Load instructions have an “update” form, in which register RA is -->
  24 <!-- updated with the effective address. For these forms, if RA!=0 and RA!=RT, the -->
  25 <!-- effective address is placed into register RA and the storage element (byte, -->
  26 <!-- halfword, word, or doubleword) addressed by EA is loaded into RT. -->
  27
  28
  29 # Load Byte and Zero Shifted Indexed
  30
  31 X-Form
  32
  33 * lbzsx RT,RA,RB,SH
  34
  35 Pseudo-code:
  36
  37     b <- (RA|0)
  38     EA <- b + (RB) << (SH+1)
  39     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  40
  41 Description:
  42
  43     Let the effective address (EA) be the sum of the contents of
  44     register RB shifted by (SH+1), and (RA|0).
  45
  46     The byte in storage addressed by EA is loaded into
  47     RT[56:63]. RT[0:55] are set to 0.
  48
  49
  50 Special Registers Altered:
  51
  52     None
  53
  54 # Load Byte and Zero Shifted with Update Indexed
  55
  56 X-Form
  57
  58 * lbzsux RT,RA,RB,SH
  59
  60 Pseudo-code:
  61
  62     EA <- (RA) + (RB) << (SH+1)
  63     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  64     RA <- EA
  65
  66 Description:
  67
  68     Let the effective address (EA) be the sum of the contents of
  69     register RB shifted by (SH+1), and (RA).
  70
  71     The byte in storage addressed by EA is
  72     loaded into RT[56:63] . RT[0:55] are set to 0.
  73
  74     EA is placed into register RA.
  75
  76     If RA=0, the instruction form is invalid.
  77
  78 Special Registers Altered:
  79
  80     None
  81
  82 # Load Halfword and Zero Shifted Indexed
  83
  84 X-Form
  85
  86 * lhzsx RT,RA,RB,SH
  87
  88 Pseudo-code:
  89
  90     b <- (RA|0)
  91     EA <- b + (RB) << (SH+1)
  92     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  93
  94 Description:
  95
  96     Let the effective address (EA) be the sum of the contents of
  97     register RB shifted by (SH+1), and (RA|0).
  98
  99     The halfword in storage addressed by EA is loaded into
 100     RT[48:63]. RT[0:47] are set to 0.
 101
 102 Special Registers Altered:
 103
 104     None
 105
 106 # Load Halfword and Zero Shifted with Update Indexed
 107
 108 X-Form
 109
 110 * lhzsux RT,RA,RB,SH
 111
 112 Pseudo-code:
 113
 114     EA <- (RA) + (RB) << (SH+1)
 115     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 116     RA <- EA
 117
 118 Description:
 119
 120     Let the effective address (EA) be the sum of the contents of
 121     register RB shifted by (SH+1), and (RA).
 122
 123     The halfword in storage addressed by EA is loaded into RT[48:63].
 124     RT[0:47] are set to 0.
 125
 126     EA is placed into register RA.
 127
 128     If RA=0, the instruction form is invalid.
 129
 130 Special Registers Altered:
 131
 132     None
 133
 134 # Load Halfword Algebraic Shifted Indexed
 135
 136 X-Form
 137
 138 * lhasx RT,RA,RB,SH
 139
 140 Pseudo-code:
 141
 142     b <- (RA|0)
 143     EA <- b + (RB) << (SH+1)
 144     RT <- EXTS(MEM(EA, 2))
 145
 146 Special Registers Altered:
 147
 148     None
 149
 150 # Load Halfword Algebraic Shifted with Update Indexed
 151
 152 X-Form
 153
 154 * lhasux RT,RA,RB,SH
 155
 156 Pseudo-code:
 157
 158     EA <- (RA) + (RB) << (SH+1)
 159     RT <- EXTS(MEM(EA, 2))
 160     RA <- EA
 161
 162 Special Registers Altered:
 163
 164     None
 165
 166 # Load Word and Zero Shifted Indexed
 167
 168 X-Form
 169
 170 * lwzsx RT,RA,RB,SH
 171
 172 Pseudo-code:
 173
 174     b <- (RA|0)
 175     EA <- b + (RB) << (SH+1)
 176     RT <- [0] * 32 || MEM(EA, 4)
 177
 178 Special Registers Altered:
 179
 180     None
 181
 182 # Load Word and Zero Shifted with Update Indexed
 183
 184 X-Form
 185
 186 * lwzsux RT,RA,RB,SH
 187
 188 Pseudo-code:
 189
 190     EA <- (RA) + (RB) << (SH+1)
 191     RT <- [0] * 32 || MEM(EA, 4)
 192     RA <- EA
 193
 194 Special Registers Altered:
 195
 196     None
 197
 198 # Load Word Algebraic Shifted Indexed
 199
 200 X-Form
 201
 202 * lwasx RT,RA,RB,SH
 203
 204 Pseudo-code:
 205
 206     b <- (RA|0)
 207     EA <- b + (RB) << (SH+1)
 208     RT <- EXTS(MEM(EA, 4))
 209
 210 Special Registers Altered:
 211
 212     None
 213
 214 # Load Word Algebraic Shifted with Update Indexed
 215
 216 X-Form
 217
 218 * lwasux RT,RA,RB,SH
 219
 220 Pseudo-code:
 221
 222     EA <- (RA) + (RB) << (SH+1)
 223     RT <- EXTS(MEM(EA, 4))
 224     RA <- EA
 225
 226 Special Registers Altered:
 227
 228     None
 229
 230 # Load Doubleword Shifted Indexed
 231
 232 X-Form
 233
 234 * ldsx RT,RA,RB,SH
 235
 236 Pseudo-code:
 237
 238     b <- (RA|0)
 239     EA <- b + (RB) << (SH+1)
 240     RT <- MEM(EA, 8)
 241
 242 Special Registers Altered:
 243
 244     None
 245
 246 # Load Doubleword Shifted with Update Indexed
 247
 248 X-Form
 249
 250 * ldsux RT,RA,RB,SH
 251
 252 Pseudo-code:
 253
 254     EA <- (RA) + (RB) << (SH+1)
 255     RT <- MEM(EA, 8)
 256     RA <- EA
 257
 258 Special Registers Altered:
 259
 260     None
 261
 262 <!-- byte-reverse shifted -->
 263
 264 # Load Halfword Byte-Reverse Shifted Indexed
 265
 266 X-Form
 267
 268 * lhbrsx RT,RA,RB,SH
 269
 270 Pseudo-code:
 271
 272     b <- (RA|0)
 273     EA <- b + (RB) << (SH+1)
 274     load_data <- MEM(EA, 2)
 275     RT <- [0]*48 || load_data[8:15] || load_data[0:7]
 276
 277 Special Registers Altered:
 278
 279     None
 280
 281 # Load Word Byte-Reverse Shifted Indexed
 282
 283 X-Form
 284
 285 * lwbrsx RT,RA,RB,SH
 286
 287 Pseudo-code:
 288
 289     b <- (RA|0)
 290     EA <- b + (RB) << (SH+1)
 291     load_data <- MEM(EA, 4)
 292     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
 293                     || load_data[8:15]  || load_data[0:7])
 294
 295 Special Registers Altered:
 296
 297     None
 298
 299
 300 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 301
 302 # Load Doubleword Byte-Reverse Shifted Indexed
 303
 304 X-Form
 305
 306 * ldbrsx RT,RA,RB,SH
 307
 308 Pseudo-code:
 309
 310     b <- (RA|0)
 311     EA <- b + (RB) << (SH+1)
 312     load_data <- MEM(EA, 8)
 313     RT <- (load_data[56:63] || load_data[48:55]
 314         || load_data[40:47] || load_data[32:39]
 315         || load_data[24:31] || load_data[16:23]
 316         || load_data[8:15]  || load_data[0:7])
 317
 318 Special Registers Altered:
 319
 320     None
 321