1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- Section 3.3.13 Fixed-Point Logical Instructions page 92 - 100 -->
5 <!-- The Logical instructions perform bit-parallel operations on 64-bit operands. -->
7 <!-- The X-form Logical instructions with Rc=1, and the D-form Logical instructions -->
8 <!-- andi. and andis., set the first three bits of CR Field 0 as described in -->
9 <!-- Section 3.3.8, “Other Fixed-Point Instructions” on page 66. The Logical -->
10 <!-- instructions do not change the SO, OV, OV32, CA, and CA32 bits in the XER. -->
23 Special Registers Altered:
37 Special Registers Altered:
41 # AND Immediate Shifted
49 RA <- (RS) & EXTZ(UI || [0]*16)
51 Special Registers Altered:
55 # OR Immediate Shifted
63 RA <- (RS) | EXTZ(UI || [0]*16)
65 Special Registers Altered:
69 # XOR Immediate Shifted
77 RA <- (RS) ^ EXTZ(UI || [0]*16)
79 Special Registers Altered:
93 Special Registers Altered:
101 * and RA,RS,RB (Rc=0)
102 * and. RA,RS,RB (Rc=1)
108 Special Registers Altered:
117 * or. RA,RS,RB (Rc=1)
123 Special Registers Altered:
131 * xor RA,RS,RB (Rc=0)
132 * xor. RA,RS,RB (Rc=1)
138 Special Registers Altered:
146 * nand RA,RS,RB (Rc=0)
147 * nand. RA,RS,RB (Rc=1)
153 Special Registers Altered:
161 * nor RA,RS,RB (Rc=0)
162 * nor. RA,RS,RB (Rc=1)
168 Special Registers Altered:
176 * eqv RA,RS,RB (Rc=0)
177 * eqv. RA,RS,RB (Rc=1)
183 Special Registers Altered:
187 # AND with Complement
191 * andc RA,RS,RB (Rc=0)
192 * andc. RA,RS,RB (Rc=1)
198 Special Registers Altered:
206 * orc RA,RS,RB (Rc=0)
207 * orc. RA,RS,RB (Rc=1)
213 Special Registers Altered:
222 * extsb. RA,RS (Rc=1)
226 RA <- EXTSXL(RS, XLEN/8)
228 Special Registers Altered:
232 # Extend Sign Halfword
237 * extsh. RA,RS (Rc=1)
241 RA <- EXTSXL(RS, XLEN/4)
243 Special Registers Altered:
247 # Count Leading Zeros Word
251 * cntlzw RA,RS (Rc=0)
252 * cntlzw. RA,RS (Rc=1)
263 Special Registers Altered:
267 # Count Trailing Zeros Word
271 * cnttzw RA,RS (Rc=0)
272 * cnttzw. RA,RS (Rc=1)
278 if (RS)[XLEN-1-n] = 0b1 then
283 Special Registers Altered:
295 do n = 0 to ((XLEN/8)-1)
296 if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then
297 RA[8*n:8* n+7] <- [1]*8
299 RA[8*n:8* n+7] <- [0]*8
301 Special Registers Altered:
305 # Population Count Bytes
313 do i = 0 to ((XLEN/8)-1)
316 if (RS)[(i*8)+j] = 1 then
318 RA[(i*8):(i*8)+7] <- n
320 Special Registers Altered:
324 # Population Count Words
337 if (RS)[s+j] = 1 then
341 Special Registers Altered:
354 do i = 0 to ((XLEN/8)-1)
356 RA <- [0] * (XLEN-1) || s
358 Special Registers Altered:
372 do i = 0 to ((XLEN/8/2)-1)
374 do i = 4 to ((XLEN/8)-1)
376 RA[0:(XLEN/2)-1] <- [0]*((XLEN/2)-1) || s
377 RA[XLEN/2:XLEN-1] <- [0]*((XLEN/2)-1) || t
379 Special Registers Altered:
388 * extsw. RA,RS (Rc=1)
392 RA <- EXTSXL(RS, XLEN/2)
394 Special Registers Altered:
398 # Population Count Doubleword
412 Special Registers Altered:
416 # Count Leading Zeros Doubleword
420 * cntlzd RA,RS (Rc=0)
421 * cntlzd. RA,RS (Rc=1)
432 Special Registers Altered:
436 # Count Trailing Zeros Doubleword
440 * cnttzd RA,RS (Rc=0)
441 * cnttzd. RA,RS (Rc=1)
447 if (RS)[XLEN-1-n] = 0b1 then
452 Special Registers Altered:
456 # Count Leading Zeros Doubleword under bit Mask
467 if (RS)[i] = 1 then leave
471 Special Registers Altered:
475 # Count Trailing Zeros Doubleword under bit Mask
485 if (RB)[63-i] = 1 then
486 if (RS)[63-i] = 1 then leave
490 Special Registers Altered:
494 # Bit Permute Doubleword
502 perm <- [0] * (XLEN/8)
503 for i = 0 to ((XLEN/8)-1)
504 index <- (RS)[8*i:8*i+7]
505 if index <u XLEN then
506 perm[i] <- (RB)[index]
509 RA <- [0]*(XLEN*7/8) || perm
511 Special Registers Altered:
515 # Centrifuge Doubleword
528 result[ptr0] <- (RS)[i]
530 if (RB)[63-i] = 1 then
531 result[63-ptr1] <- (RS)[63-i]
535 Special Registers Altered:
539 # Parallel Bits Extract Doubleword
552 if (RB)[63-m] = 1 then
553 result[63-k] <- (RS)[63-m]
558 Special Registers Altered:
562 # Parallel Bits Deposit Doubleword
575 if (RB)[63-m] = 1 then
576 result[63-m] <- (RS)[63-k]
581 Special Registers Altered: