fixedlogical: switch andi. to XLCASTU
[openpower-isa.git] / openpower / isa / fixedlogical.mdwn
1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
2
3 <!-- Section 3.3.13 Fixed-Point Logical Instructions page 92 - 100 -->
4
5 <!-- The Logical instructions perform bit-parallel operations on 64-bit operands. -->
6
7 <!-- The X-form Logical instructions with Rc=1, and the D-form Logical instructions -->
8 <!-- andi. and andis., set the first three bits of CR Field 0 as described in -->
9 <!-- Section 3.3.8, “Other Fixed-Point Instructions” on page 66. The Logical -->
10 <!-- instructions do not change the SO, OV, OV32, CA, and CA32 bits in the XER. -->
11
12
13 # AND Immediate
14
15 D-Form
16
17 * andi. RA,RS,UI
18
19 Pseudo-code:
20
21 RA <- (RS) & XLCASTU(UI)
22
23 Special Registers Altered:
24
25 CR0
26
27 # OR Immediate
28
29 D-Form
30
31 * ori RA,RS,UI
32
33 Pseudo-code:
34
35 RA <- (RS) | ([0]*(XLEN-16) || UI)
36
37 Special Registers Altered:
38
39 None
40
41 # AND Immediate Shifted
42
43 D-Form
44
45 * andis. RA,RS,UI
46
47 Pseudo-code:
48
49 RA <- (RS) & ([0]*(XLEN-32) || UI || [0]*16)
50
51 Special Registers Altered:
52
53 CR0
54
55 # OR Immediate Shifted
56
57 D-Form
58
59 * oris RA,RS,UI
60
61 Pseudo-code:
62
63 RA <- (RS) | ([0]*(XLEN-32) || UI || [0]*16)
64
65 Special Registers Altered:
66
67 None
68
69 # XOR Immediate Shifted
70
71 D-Form
72
73 * xoris RA,RS,UI
74
75 Pseudo-code:
76
77 RA <- (RS) ^ ([0]*(XLEN-32) || UI || [0]*16)
78
79 Special Registers Altered:
80
81 None
82
83 # XOR Immediate
84
85 D-Form
86
87 * xori RA,RS,UI
88
89 Pseudo-code:
90
91 RA <- (RS) ^ ([0]*(XLEN-16) || UI)
92
93 Special Registers Altered:
94
95 None
96
97 # AND
98
99 X-Form
100
101 * and RA,RS,RB (Rc=0)
102 * and. RA,RS,RB (Rc=1)
103
104 Pseudo-code:
105
106 RA <- (RS) & (RB)
107
108 Special Registers Altered:
109
110 CR0 (if Rc=1)
111
112 # OR
113
114 X-Form
115
116 * or RA,RS,RB (Rc=0)
117 * or. RA,RS,RB (Rc=1)
118
119 Pseudo-code:
120
121 RA <- (RS) | (RB)
122
123 Special Registers Altered:
124
125 CR0 (if Rc=1)
126
127 # XOR
128
129 X-Form
130
131 * xor RA,RS,RB (Rc=0)
132 * xor. RA,RS,RB (Rc=1)
133
134 Pseudo-code:
135
136 RA <- (RS) ^ (RB)
137
138 Special Registers Altered:
139
140 CR0 (if Rc=1)
141
142 # NAND
143
144 X-Form
145
146 * nand RA,RS,RB (Rc=0)
147 * nand. RA,RS,RB (Rc=1)
148
149 Pseudo-code:
150
151 RA <- ¬((RS) & (RB))
152
153 Special Registers Altered:
154
155 CR0 (if Rc=1)
156
157 # NOR
158
159 X-Form
160
161 * nor RA,RS,RB (Rc=0)
162 * nor. RA,RS,RB (Rc=1)
163
164 Pseudo-code:
165
166 RA <- ¬((RS) | (RB))
167
168 Special Registers Altered:
169
170 CR0 (if Rc=1)
171
172 # Equivalent
173
174 X-Form
175
176 * eqv RA,RS,RB (Rc=0)
177 * eqv. RA,RS,RB (Rc=1)
178
179 Pseudo-code:
180
181 RA <- ¬((RS) ^ (RB))
182
183 Special Registers Altered:
184
185 CR0 (if Rc=1)
186
187 # AND with Complement
188
189 X-Form
190
191 * andc RA,RS,RB (Rc=0)
192 * andc. RA,RS,RB (Rc=1)
193
194 Pseudo-code:
195
196 RA <- (RS) & ¬(RB)
197
198 Special Registers Altered:
199
200 CR0 (if Rc=1)
201
202 # OR with Complement
203
204 X-Form
205
206 * orc RA,RS,RB (Rc=0)
207 * orc. RA,RS,RB (Rc=1)
208
209 Pseudo-code:
210
211 RA <- (RS) | ¬(RB)
212
213 Special Registers Altered:
214
215 CR0 (if Rc=1)
216
217 # Extend Sign Byte
218
219 X-Form
220
221 * extsb RA,RS (Rc=0)
222 * extsb. RA,RS (Rc=1)
223
224 Pseudo-code:
225
226 s <- (RS)[56]
227 RA[56:63] <- (RS)[56:63]
228 RA[0:55] <- [s]*56
229
230 Special Registers Altered:
231
232 CR0 (if Rc=1)
233
234 # Extend Sign Halfword
235
236 X-Form
237
238 * extsh RA,RS (Rc=0)
239 * extsh. RA,RS (Rc=1)
240
241 Pseudo-code:
242
243 s <- (RS)[48]
244 RA[48:63] <- (RS)[48:63]
245 RA[0:47] <- [s]*48
246
247 Special Registers Altered:
248
249 CR0 (if Rc=1)
250
251 # Count Leading Zeros Word
252
253 X-Form
254
255 * cntlzw RA,RS (Rc=0)
256 * cntlzw. RA,RS (Rc=1)
257
258 Pseudo-code:
259
260 n <- (XLEN/2)
261 do while n < XLEN
262 if (RS)[n] = 1 then
263 leave
264 n <- n + 1
265 RA <- n - (XLEN/2)
266
267 Special Registers Altered:
268
269 CR0 (if Rc=1)
270
271 # Count Trailing Zeros Word
272
273 X-Form
274
275 * cnttzw RA,RS (Rc=0)
276 * cnttzw. RA,RS (Rc=1)
277
278 Pseudo-code:
279
280 n <- 0
281 do while n < 32
282 if (RS)[63-n] = 0b1 then
283 leave
284 n <- n + 1
285 RA <- EXTZ64(n)
286
287 Special Registers Altered:
288
289 CR0 (if Rc=1)
290
291 # Compare Bytes
292
293 X-Form
294
295 * cmpb RA,RS,RB
296
297 Pseudo-code:
298
299 do n = 0 to ((XLEN/8)-1)
300 if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then
301 RA[8*n:8* n+7] <- [1]*8
302 else
303 RA[8*n:8* n+7] <- [0]*8
304
305 Special Registers Altered:
306
307 None
308
309 # Population Count Bytes
310
311 X-Form
312
313 * popcntb RA, RS
314
315 Pseudo-code:
316
317 do i = 0 to ((XLEN/8)-1)
318 n <- 0
319 do j = 0 to 7
320 if (RS)[(i*8)+j] = 1 then
321 n <- n+1
322 RA[(i*8):(i*8)+7] <- n
323
324 Special Registers Altered:
325
326 None
327
328 # Population Count Words
329
330 X-Form
331
332 * popcntw RA, RS
333
334 Pseudo-code:
335
336 e <- (XLEN/2)-1
337 do i = 0 to 1
338 s <- i*XLEN/2
339 n <- 0
340 do j = 0 to e
341 if (RS)[s+j] = 1 then
342 n <- n+1
343 RA[s:s+e] <- n
344
345 Special Registers Altered:
346
347 None
348
349 # Parity Doubleword
350
351 X-Form
352
353 * prtyd RA,RS
354
355 Pseudo-code:
356
357 s <- 0
358 do i = 0 to ((XLEN/8)-1)
359 s <- s ^ (RS)[i*8+7]
360 RA <- [0] * (XLEN-1) || s
361
362 Special Registers Altered:
363
364 None
365
366 # Parity Word
367
368 X-Form
369
370 * prtyw RA,RS
371
372 Pseudo-code:
373
374 s <- 0
375 t <- 0
376 do i = 0 to ((XLEN/8/2)-1)
377 s <- s ^ (RS)[i*8+7]
378 do i = 4 to ((XLEN/8)-1)
379 t <- t ^ (RS)[i*8+7]
380 RA[0:(XLEN/2)-1] <- [0]*((XLEN/2)-1) || s
381 RA[XLEN/2:XLEN-1] <- [0]*((XLEN/2)-1) || t
382
383 Special Registers Altered:
384
385 None
386
387 # Extend Sign Word
388
389 X-Form
390
391 * extsw RA,RS (Rc=0)
392 * extsw. RA,RS (Rc=1)
393
394 Pseudo-code:
395
396 s <- (RS)[XLEN/2]
397 RA[XLEN/2:XLEN-1] <- (RS)[XLEN/2:XLEN-1]
398 RA[0:(XLEN/2)-1] <- [s]*(XLEN/2)
399
400 Special Registers Altered:
401
402 CR0 (if Rc=1)
403
404 # Population Count Doubleword
405
406 X-Form
407
408 * popcntd RA, RS
409
410 Pseudo-code:
411
412 n <- 0
413 do i = 0 to (XLEN-1)
414 if (RS)[i] = 1 then
415 n <- n+1
416 RA <- n
417
418 Special Registers Altered:
419
420 None
421
422 # Count Leading Zeros Doubleword
423
424 X-Form
425
426 * cntlzd RA,RS (Rc=0)
427 * cntlzd. RA,RS (Rc=1)
428
429 Pseudo-code:
430
431 n <- 0
432 do while n < XLEN
433 if (RS)[n] = 1 then
434 leave
435 n <- n + 1
436 RA <- n
437
438 Special Registers Altered:
439
440 CR0 (if Rc=1)
441
442 # Count Trailing Zeros Doubleword
443
444 X-Form
445
446 * cnttzd RA,RS (Rc=0)
447 * cnttzd. RA,RS (Rc=1)
448
449 Pseudo-code:
450
451 n <- 0
452 do while n < XLEN
453 if (RS)[XLEN-1-n] = 0b1 then
454 leave
455 n <- n + 1
456 RA <- EXTZ64(n)
457
458 Special Registers Altered:
459
460 CR0 (if Rc=1)
461
462 # Bit Permute Doubleword
463
464 X-Form
465
466 * bpermd RA,RS,RB]
467
468 Pseudo-code:
469
470 perm <- [0] * 8
471 for i = 0 to ((XLEN/8)-1)
472 index <- (RS)[8*i:8*i+7]
473 if index <u XLEN then
474 perm[i] <- (RB)[index]
475 else
476 perm[i] <- 0
477 RA <- [0]*(XLEN-8) || perm[0:7]
478
479 Special Registers Altered:
480
481 None
482
483 <!-- Checked March 2021 -->