1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- Section 3.3.13 Fixed-Point Logical Instructions page 92 - 100 -->
5 <!-- The Logical instructions perform bit-parallel operations on 64-bit operands. -->
7 <!-- The X-form Logical instructions with Rc=1, and the D-form Logical instructions -->
8 <!-- andi. and andis., set the first three bits of CR Field 0 as described in -->
9 <!-- Section 3.3.8, “Other Fixed-Point Instructions” on page 66. The Logical -->
10 <!-- instructions do not change the SO, OV, OV32, CA, and CA32 bits in the XER. -->
21 RA <- (RS) & XLCASTU(UI)
23 Special Registers Altered:
35 RA <- (RS) | ([0]*(XLEN-16) || UI)
37 Special Registers Altered:
41 # AND Immediate Shifted
49 RA <- (RS) & ([0]*(XLEN-32) || UI || [0]*16)
51 Special Registers Altered:
55 # OR Immediate Shifted
63 RA <- (RS) | ([0]*(XLEN-32) || UI || [0]*16)
65 Special Registers Altered:
69 # XOR Immediate Shifted
77 RA <- (RS) ^ ([0]*(XLEN-32) || UI || [0]*16)
79 Special Registers Altered:
91 RA <- (RS) ^ ([0]*(XLEN-16) || UI)
93 Special Registers Altered:
101 * and RA,RS,RB (Rc=0)
102 * and. RA,RS,RB (Rc=1)
108 Special Registers Altered:
117 * or. RA,RS,RB (Rc=1)
123 Special Registers Altered:
131 * xor RA,RS,RB (Rc=0)
132 * xor. RA,RS,RB (Rc=1)
138 Special Registers Altered:
146 * nand RA,RS,RB (Rc=0)
147 * nand. RA,RS,RB (Rc=1)
153 Special Registers Altered:
161 * nor RA,RS,RB (Rc=0)
162 * nor. RA,RS,RB (Rc=1)
168 Special Registers Altered:
176 * eqv RA,RS,RB (Rc=0)
177 * eqv. RA,RS,RB (Rc=1)
183 Special Registers Altered:
187 # AND with Complement
191 * andc RA,RS,RB (Rc=0)
192 * andc. RA,RS,RB (Rc=1)
198 Special Registers Altered:
206 * orc RA,RS,RB (Rc=0)
207 * orc. RA,RS,RB (Rc=1)
213 Special Registers Altered:
222 * extsb. RA,RS (Rc=1)
227 RA[56:63] <- (RS)[56:63]
230 Special Registers Altered:
234 # Extend Sign Halfword
239 * extsh. RA,RS (Rc=1)
244 RA[48:63] <- (RS)[48:63]
247 Special Registers Altered:
251 # Count Leading Zeros Word
255 * cntlzw RA,RS (Rc=0)
256 * cntlzw. RA,RS (Rc=1)
267 Special Registers Altered:
271 # Count Trailing Zeros Word
275 * cnttzw RA,RS (Rc=0)
276 * cnttzw. RA,RS (Rc=1)
282 if (RS)[63-n] = 0b1 then
287 Special Registers Altered:
299 do n = 0 to ((XLEN/8)-1)
300 if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then
301 RA[8*n:8* n+7] <- [1]*8
303 RA[8*n:8* n+7] <- [0]*8
305 Special Registers Altered:
309 # Population Count Bytes
317 do i = 0 to ((XLEN/8)-1)
320 if (RS)[(i*8)+j] = 1 then
322 RA[(i*8):(i*8)+7] <- n
324 Special Registers Altered:
328 # Population Count Words
341 if (RS)[s+j] = 1 then
345 Special Registers Altered:
358 do i = 0 to ((XLEN/8)-1)
360 RA <- [0] * (XLEN-1) || s
362 Special Registers Altered:
376 do i = 0 to ((XLEN/8/2)-1)
378 do i = 4 to ((XLEN/8)-1)
380 RA[0:(XLEN/2)-1] <- [0]*((XLEN/2)-1) || s
381 RA[XLEN/2:XLEN-1] <- [0]*((XLEN/2)-1) || t
383 Special Registers Altered:
392 * extsw. RA,RS (Rc=1)
397 RA[XLEN/2:XLEN-1] <- (RS)[XLEN/2:XLEN-1]
398 RA[0:(XLEN/2)-1] <- [s]*(XLEN/2)
400 Special Registers Altered:
404 # Population Count Doubleword
418 Special Registers Altered:
422 # Count Leading Zeros Doubleword
426 * cntlzd RA,RS (Rc=0)
427 * cntlzd. RA,RS (Rc=1)
438 Special Registers Altered:
442 # Count Trailing Zeros Doubleword
446 * cnttzd RA,RS (Rc=0)
447 * cnttzd. RA,RS (Rc=1)
453 if (RS)[XLEN-1-n] = 0b1 then
458 Special Registers Altered:
462 # Bit Permute Doubleword
471 for i = 0 to ((XLEN/8)-1)
472 index <- (RS)[8*i:8*i+7]
473 if index <u XLEN then
474 perm[i] <- (RB)[index]
477 RA <- [0]*(XLEN-8) || perm[0:7]
479 Special Registers Altered:
483 <!-- Checked March 2021 -->