openpower/isa/fixedstore.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte
  18
  19 D-Form
  20
  21 * stb RS,D(RA)
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + EXTS(D)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31     Let the effective address (EA) be the sum (RA|0)+ D.
  32     RS[56:63] are stored into the byte in storage addressed
  33     by EA.
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Store Byte Indexed
  40
  41 X-Form
  42
  43 * stbx RS,RA,RB
  44
  45 Pseudo-code:
  46
  47     b <- (RA|0)
  48     EA <- b + (RB)
  49     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  50
  51 Description:
  52
  53     Let the effective address (EA) be the sum
  54     (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
  55     age addressed by EA.
  56
  57 Special Registers Altered:
  58
  59     None
  60
  61 # Store Byte with Update
  62
  63 D-Form
  64
  65 * stbu RS,D(RA)
  66
  67 Pseudo-code:
  68
  69     EA <- (RA) + EXTS(D)
  70     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  71     RA <- EA
  72
  73 Description:
  74
  75     Let the effective address (EA) be the sum (RA)+ D.
  76     RS[56:63] are stored into the byte in storage addressed
  77     by EA.
  78
  79     EA is placed into register RA.
  80
  81     If RA=0, the instruction form is invalid.
  82
  83 Special Registers Altered:
  84
  85     None
  86
  87 # Store Byte with Update Indexed
  88
  89 X-Form
  90
  91 * stbux RS,RA,RB
  92
  93 Pseudo-code:
  94
  95     EA <- (RA) + (RB)
  96     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  97     RA <- EA
  98
  99 Description:
 100
 101     Let the effective address (EA) be the sum (RA)+ (RB).
 102     RS[56:63] are stored into the byte in storage addressed
 103     by EA.
 104
 105     EA is placed into register RA.
 106
 107     If RA=0, the instruction form is invalid.
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Store Halfword
 114
 115 D-Form
 116
 117 * sth RS,D(RA)
 118
 119 Pseudo-code:
 120
 121     b <- (RA|0)
 122     EA <- b + EXTS(D)
 123     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 124
 125 Description:
 126
 127     Let the effective address (EA) be the sum (RA|0)+ D.
 128     RS[48:63] are stored into the halfword in storage
 129     addressed by EA.
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Store Halfword Indexed
 136
 137 X-Form
 138
 139 * sthx RS,RA,RB
 140
 141 Pseudo-code:
 142
 143     b <- (RA|0)
 144     EA <- b + (RB)
 145     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 146
 147 Description:
 148
 149     Let the effective address (EA) be the sum
 150     (RA|0)+ (RB). RS[48:63] are stored into the halfword in
 151     storage addressed by EA.
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Store Halfword with Update
 158
 159 D-Form
 160
 161 * sthu RS,D(RA)
 162
 163 Pseudo-code:
 164
 165     EA <- (RA) + EXTS(D)
 166     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 167     RA <- EA
 168
 169 Description:
 170
 171     Let the effective address (EA) be the sum (RA)+ D.
 172     RS[48:63] are stored into the halfword in storage
 173     addressed by EA.
 174
 175     EA is placed into register RA.
 176
 177     If RA=0, the instruction form is invalid.
 178
 179 Special Registers Altered:
 180
 181     None
 182
 183 # Store Halfword with Update Indexed
 184
 185 X-Form
 186
 187 * sthux RS,RA,RB
 188
 189 Pseudo-code:
 190
 191     EA <- (RA) + (RB)
 192     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 193     RA <- EA
 194
 195 Description:
 196
 197     Let the effective address (EA) be the sum (RA)+ (RB).
 198     RS[48:63] are stored into the halfword in storage
 199     addressed by EA.
 200
 201     EA is placed into register RA.
 202
 203     If RA=0, the instruction form is invalid.
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Store Word
 210
 211 D-Form
 212
 213 * stw RS,D(RA)
 214
 215 Pseudo-code:
 216
 217     b <- (RA|0)
 218     EA <- b + EXTS(D)
 219     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 220
 221 Description:
 222
 223     Let the effective address (EA) be the sum (RA|0)+ D.
 224     RS[32:63] are stored into the word in storage addressed
 225     by EA.
 226
 227 Special Registers Altered:
 228
 229     None
 230
 231 # Store Word Indexed
 232
 233 X-Form
 234
 235 * stwx RS,RA,RB
 236
 237 Pseudo-code:
 238
 239     b <- (RA|0)
 240     EA <- b + (RB)
 241     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 242
 243 Description:
 244
 245     Let the effective address (EA) be the sum
 246     (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
 247     age addressed by EA.
 248
 249 Special Registers Altered:
 250
 251     None
 252
 253 # Store Word with Update
 254
 255 D-Form
 256
 257 * stwu RS,D(RA)
 258
 259 Pseudo-code:
 260
 261     EA <- (RA) + EXTS(D)
 262     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 263     RA <- EA
 264
 265 Description:
 266
 267     Let the effective address (EA) be the sum (RA)+ D.
 268     RS[32:63] are stored into the word in storage addressed
 269     by EA.
 270
 271     EA is placed into register RA.
 272
 273     If RA=0, the instruction form is invalid.
 274
 275 Special Registers Altered:
 276
 277     None
 278
 279 # Store Word with Update Indexed
 280
 281 X-Form
 282
 283 * stwux RS,RA,RB
 284
 285 Pseudo-code:
 286
 287     EA <- (RA) + (RB)
 288     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 289     RA <- EA
 290
 291 Description:
 292
 293     Let the effective address (EA) be the sum (RA)+ (RB).
 294     RS[32:63] are stored into the word in storage addressed
 295     by EA.
 296
 297     EA is placed into register RA.
 298
 299     If RA=0, the instruction form is invalid.
 300
 301 Special Registers Altered:
 302
 303     None
 304
 305
 306
 307 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 308
 309 # Store Doubleword
 310
 311 DS-Form
 312
 313 * std RS,DS(RA)
 314
 315 Pseudo-code:
 316
 317     b <- (RA|0)
 318     EA <- b + EXTS(DS || 0b00)
 319     MEM(EA, 8) <- (RS)
 320
 321 Description:
 322
 323     Let the effective address (EA) be the sum
 324     (RA|0)+ (DS||0b00). (RS) is stored into the doubleword
 325     in storage addressed by EA.
 326
 327 Special Registers Altered:
 328
 329     None
 330
 331 # Store Doubleword Indexed
 332
 333 X-Form
 334
 335 * stdx RS,RA,RB
 336
 337 Pseudo-code:
 338
 339     b <- (RA|0)
 340     EA <- b + (RB)
 341     MEM(EA, 8) <- (RS)
 342
 343 Description:
 344
 345     Let the effective address (EA) be the sum
 346     (RA|0)+ (RB). (RS) is stored into the doubleword in
 347     storage addressed by EA.
 348
 349 Special Registers Altered:
 350
 351     None
 352
 353 # Store Doubleword with Update
 354
 355 DS-Form
 356
 357 * stdu RS,DS(RA)
 358
 359 Pseudo-code:
 360
 361     EA <- (RA) + EXTS(DS || 0b00)
 362     MEM(EA, 8) <- (RS)
 363     RA <- EA
 364
 365 Description:
 366
 367     Let the effective address (EA) be the sum
 368     (RA)+ (DS||0b00). (RS) is stored into the doubleword in
 369     storage addressed by EA.
 370
 371     EA is placed into register RA.
 372
 373     If RA=0, the instruction form is invalid.
 374
 375 Special Registers Altered:
 376
 377     None
 378
 379 # Store Doubleword with Update Indexed
 380
 381 X-Form
 382
 383 * stdux RS,RA,RB
 384
 385 Pseudo-code:
 386
 387     EA <- (RA) + (RB)
 388     MEM(EA, 8) <- (RS)
 389     RA <- EA
 390
 391 Description:
 392
 393     Let the effective address (EA) be the sum (RA)+ (RB).
 394     (RS) is stored into the doubleword in storage
 395     addressed by EA.
 396
 397     EA is placed into register RA.
 398
 399     If RA=0, the instruction form is invalid.
 400
 401 Special Registers Altered:
 402
 403     None
 404
 405
 406 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 407
 408 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
 409 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
 410 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
 411 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
 412 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
 413 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
 414 <!-- byte-reversed into the doubleword addressed by EA. -->
 415
 416
 417 # Store Quadword
 418
 419 DS-Form
 420
 421 * stq RSp,DS(RA)
 422
 423 Pseudo-code:
 424
 425     b <- (RA|0)
 426     EA <- b + EXTS(DS || 0b00)
 427     MEM(EA, 16) <- RSp
 428
 429 Description:
 430
 431     Let the effective address (EA) be the sum (RA|0)+
 432     (DS||0b00). The contents of register pair RSp are
 433     stored into the quadword in storage addressed by EA.
 434
 435     If RSp is odd, the instruction form is invalid.
 436
 437     The contents of an even-odd pair of GPRs is stored into
 438     the quadword in storage addressed by EA as follows.
 439     In Big-Endian mode, the even-numbered GPR is stored
 440     into the doubleword in storage addressed by EA and
 441     the odd-numbered GPR is stored into the doubleword
 442     addressed by EA+8. In Little-Endian mode, the
 443     even-numbered GPR is stored byte-reversed into the
 444     doubleword in storage addressed by EA+8 and the
 445     odd-numbered GPR is stored byte-reversed into the
 446     doubleword addressed by EA.
 447
 448 Special Registers Altered:
 449
 450     None
 451
 452 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 453
 454 # Store Halfword Byte-Reverse Indexed
 455
 456 X-Form
 457
 458 * sthbrx RS,RA,RB
 459
 460 Pseudo-code:
 461
 462     b <- (RA|0)
 463     EA <- b + (RB)
 464     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 465
 466 Description:
 467
 468     Let the effective address (EA) be the sum
 469     (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
 470     halfword in storage addressed by EA. (RS) 48:55 are
 471     stored into bits 8:15 of the halfword in storage
 472     addressed by EA.
 473
 474 Special Registers Altered:
 475
 476     None
 477
 478 # Store Word Byte-Reverse Indexed
 479
 480 X-Form
 481
 482 * stwbrx RS,RA,RB
 483
 484 Pseudo-code:
 485
 486     b <- (RA|0)
 487     EA <- b + (RB)
 488     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 489                    ||(RS)[32:39])
 490
 491 Description:
 492
 493     Let the effective address (EA) be the sum
 494     (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
 495     word in storage addressed by EA. (RS) [48:55] are stored
 496     into bits 8:15 of the word in storage addressed by EA.
 497     (RS)[40:47] are stored into bits 16:23 of the word in stor-
 498     age addressed by EA. (RS) [32:39] are stored into bits
 499     24:31 of the word in storage addressed by EA.
 500
 501 Special Registers Altered:
 502
 503     None
 504
 505 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 506
 507 # Store Doubleword Byte-Reverse Indexed
 508
 509 X-Form
 510
 511 * stdbrx RS,RA,RB
 512
 513 Pseudo-code:
 514
 515     b <- (RA|0)
 516     EA <- b + (RB)
 517     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 518                     || (RS)[40:47] || (RS)[32:39]
 519                     || (RS)[24:31] || (RS)[16:23]
 520                     || (RS)[8:15]  || (RS)[0:7])
 521
 522 Description:
 523
 524     Let the effective address (EA) be the sum
 525     (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
 526     doubleword in storage addressed by EA. (RS) [48:55] are
 527     stored into bits 8:15 of the doubleword in storage
 528     addressed by EA. (RS) [40:47] are stored into bits 16:23 of
 529     the doubleword in storage addressed by EA. (RS) [32:39]
 530     are stored into bits 23:31 of the doubleword in storage
 531     addressed by EA. (RS) [24:31] are stored into bits 32:39 of
 532     the doubleword in storage addressed by EA. (RS) [16:23]
 533     are stored into bits 40:47 of the doubleword in storage
 534     addressed by EA. (RS)[8:15] are stored into bits 48:55 of
 535     the doubleword in storage addressed by EA. (RS) [0:7]
 536     are stored into bits 56:63 of the doubleword in storage
 537     addressed by EA.
 538
 539 Special Registers Altered:
 540
 541     None
 542
 543
 544 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 545
 546 # Store Multiple Word
 547
 548 D-Form
 549
 550 * stmw RS,D(RA)
 551
 552 Pseudo-code:
 553
 554     b <- (RA|0)
 555     EA <- b + EXTS(D)
 556     r <- RS[0:63]
 557     do while r <= 31
 558         MEM(EA, 4) <- GPR(r)[32:63]
 559         r <-  r + 1
 560         EA <-  EA + 4
 561
 562 Description:
 563
 564     Let n = (32-RS). Let the effective address (EA) be the
 565     sum (RA|0)+ D.
 566
 567     n consecutive words starting at EA are stored from the
 568     low-order 32 bits of GPRs RS through 31.
 569
 570     This instruction is not supported in Little-Endian mode.
 571     If it is executed in Little-Endian mode, the system align-
 572     ment error handler is invoked.
 573
 574 Special Registers Altered:
 575
 576     None
 577
 578 <!-- Checked March 2021 -->