1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that store from a register to RAM -->
5 <!-- Note that these pages also define equivalent load instructions, -->
6 <!-- these are described in fixedload.mdwn -->
8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
27 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
31 Let the effective address (EA) be the sum (RA|0)+ D.
32 RS[56:63] are stored into the byte in storage addressed
35 Special Registers Altered:
49 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
53 Let the effective address (EA) be the sum
54 (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
57 Special Registers Altered:
61 # Store Byte with Update
70 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
75 Let the effective address (EA) be the sum (RA)+ D.
76 RS[56:63] are stored into the byte in storage addressed
79 EA is placed into register RA.
81 If RA=0, the instruction form is invalid.
83 Special Registers Altered:
87 # Store Byte with Update Indexed
96 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
101 Let the effective address (EA) be the sum (RA)+ (RB).
102 RS[56:63] are stored into the byte in storage addressed
105 EA is placed into register RA.
107 If RA=0, the instruction form is invalid.
109 Special Registers Altered:
123 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
127 Let the effective address (EA) be the sum (RA|0)+ D.
128 RS[48:63] are stored into the halfword in storage
131 Special Registers Altered:
135 # Store Halfword Indexed
145 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
149 Let the effective address (EA) be the sum
150 (RA|0)+ (RB). RS[48:63] are stored into the halfword in
151 storage addressed by EA.
153 Special Registers Altered:
157 # Store Halfword with Update
166 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
171 Let the effective address (EA) be the sum (RA)+ D.
172 RS[48:63] are stored into the halfword in storage
175 EA is placed into register RA.
177 If RA=0, the instruction form is invalid.
179 Special Registers Altered:
183 # Store Halfword with Update Indexed
192 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
197 Let the effective address (EA) be the sum (RA)+ (RB).
198 RS[48:63] are stored into the halfword in storage
201 EA is placed into register RA.
203 If RA=0, the instruction form is invalid.
205 Special Registers Altered:
219 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
223 Let the effective address (EA) be the sum (RA|0)+ D.
224 RS[32:63] are stored into the word in storage addressed
227 Special Registers Altered:
241 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
245 Let the effective address (EA) be the sum
246 (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
249 Special Registers Altered:
253 # Store Word with Update
262 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
267 Let the effective address (EA) be the sum (RA)+ D.
268 RS[32:63] are stored into the word in storage addressed
271 EA is placed into register RA.
273 If RA=0, the instruction form is invalid.
275 Special Registers Altered:
279 # Store Word with Update Indexed
288 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
293 Let the effective address (EA) be the sum (RA)+ (RB).
294 RS[32:63] are stored into the word in storage addressed
297 EA is placed into register RA.
299 If RA=0, the instruction form is invalid.
301 Special Registers Altered:
307 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
318 EA <- b + EXTS(DS || 0b00)
323 Let the effective address (EA) be the sum
324 (RA|0)+ (DS||0b00). (RS) is stored into the doubleword
325 in storage addressed by EA.
327 Special Registers Altered:
331 # Store Doubleword Indexed
345 Let the effective address (EA) be the sum
346 (RA|0)+ (RB). (RS) is stored into the doubleword in
347 storage addressed by EA.
349 Special Registers Altered:
353 # Store Doubleword with Update
361 EA <- (RA) + EXTS(DS || 0b00)
367 Let the effective address (EA) be the sum
368 (RA)+ (DS||0b00). (RS) is stored into the doubleword in
369 storage addressed by EA.
371 EA is placed into register RA.
373 If RA=0, the instruction form is invalid.
375 Special Registers Altered:
379 # Store Doubleword with Update Indexed
393 Let the effective address (EA) be the sum (RA)+ (RB).
394 (RS) is stored into the doubleword in storage
397 EA is placed into register RA.
399 If RA=0, the instruction form is invalid.
401 Special Registers Altered:
406 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
408 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
409 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
410 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
411 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
412 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
413 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
414 <!-- byte-reversed into the doubleword addressed by EA. -->
426 EA <- b + EXTS(DS || 0b00)
431 Let the effective address (EA) be the sum (RA|0)+
432 (DS||0b00). The contents of register pair RSp are
433 stored into the quadword in storage addressed by EA.
435 If RSp is odd, the instruction form is invalid.
437 The contents of an even-odd pair of GPRs is stored into
438 the quadword in storage addressed by EA as follows.
439 In Big-Endian mode, the even-numbered GPR is stored
440 into the doubleword in storage addressed by EA and
441 the odd-numbered GPR is stored into the doubleword
442 addressed by EA+8. In Little-Endian mode, the
443 even-numbered GPR is stored byte-reversed into the
444 doubleword in storage addressed by EA+8 and the
445 odd-numbered GPR is stored byte-reversed into the
446 doubleword addressed by EA.
448 Special Registers Altered:
452 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
454 # Store Halfword Byte-Reverse Indexed
464 MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
468 Let the effective address (EA) be the sum
469 (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
470 halfword in storage addressed by EA. (RS) 48:55 are
471 stored into bits 8:15 of the halfword in storage
474 Special Registers Altered:
478 # Store Word Byte-Reverse Indexed
488 MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
493 Let the effective address (EA) be the sum
494 (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
495 word in storage addressed by EA. (RS) [48:55] are stored
496 into bits 8:15 of the word in storage addressed by EA.
497 (RS)[40:47] are stored into bits 16:23 of the word in stor-
498 age addressed by EA. (RS) [32:39] are stored into bits
499 24:31 of the word in storage addressed by EA.
501 Special Registers Altered:
505 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
507 # Store Doubleword Byte-Reverse Indexed
517 MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
518 || (RS)[40:47] || (RS)[32:39]
519 || (RS)[24:31] || (RS)[16:23]
520 || (RS)[8:15] || (RS)[0:7])
524 Let the effective address (EA) be the sum
525 (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
526 doubleword in storage addressed by EA. (RS) [48:55] are
527 stored into bits 8:15 of the doubleword in storage
528 addressed by EA. (RS) [40:47] are stored into bits 16:23 of
529 the doubleword in storage addressed by EA. (RS) [32:39]
530 are stored into bits 23:31 of the doubleword in storage
531 addressed by EA. (RS) [24:31] are stored into bits 32:39 of
532 the doubleword in storage addressed by EA. (RS) [16:23]
533 are stored into bits 40:47 of the doubleword in storage
534 addressed by EA. (RS)[8:15] are stored into bits 48:55 of
535 the doubleword in storage addressed by EA. (RS) [0:7]
536 are stored into bits 56:63 of the doubleword in storage
539 Special Registers Altered:
544 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
546 # Store Multiple Word
558 MEM(EA, 4) <- GPR(r)[32:63]
564 Let n = (32-RS). Let the effective address (EA) be the
567 n consecutive words starting at EA are stored from the
568 low-order 32 bits of GPRs RS through 31.
570 This instruction is not supported in Little-Endian mode.
571 If it is executed in Little-Endian mode, the system align-
572 ment error handler is invoked.
574 Special Registers Altered:
578 <!-- Checked March 2021 -->