openpower/isa/fixedstore.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte
  18
  19 D-Form
  20
  21 * stb RS,D(RA)
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + EXTS(D)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31 Let the effective address (EA) be the sum (RA|0)+ D.
  32 RS[56:63] are stored into the byte in storage addressed
  33 by EA.
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Store Byte Indexed
  40
  41 X-Form
  42
  43 * stbx RS,RA,RB
  44
  45 Pseudo-code:
  46
  47     b <- (RA|0)
  48     EA <- b + (RB)
  49     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  50
  51 Description:
  52
  53 Let the effective address (EA) be the sum
  54 (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
  55 age addressed by EA.
  56
  57 Special Registers Altered:
  58
  59     None
  60
  61 # Store Byte with Update
  62
  63 D-Form
  64
  65 * stbu RS,D(RA)
  66
  67 Pseudo-code:
  68
  69     EA <- (RA) + EXTS(D)
  70     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  71     RA <- EA
  72
  73 Description:
  74
  75 Let the effective address (EA) be the sum (RA)+ D.
  76 RS[56:63] are stored into the byte in storage addressed
  77 by EA.
  78
  79 EA is placed into register RA.
  80
  81 If RA=0, the instruction form is invalid.
  82
  83 Special Registers Altered:
  84
  85     None
  86
  87 # Store Byte with Update Indexed
  88
  89 X-Form
  90
  91 * stbux RS,RA,RB
  92
  93 Pseudo-code:
  94
  95     EA <- (RA) + (RB)
  96     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  97     RA <- EA
  98
  99 Description:
 100
 101 Let the effective address (EA) be the sum (RA)+ (RB).
 102 RS[56:63] are stored into the byte in storage addressed
 103 by EA.
 104
 105 EA is placed into register RA.
 106
 107 If RA=0, the instruction form is invalid.
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Store Halfword
 114
 115 D-Form
 116
 117 * sth RS,D(RA)
 118
 119 Pseudo-code:
 120
 121     b <- (RA|0)
 122     EA <- b + EXTS(D)
 123     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 124
 125 Description:
 126
 127 Let the effective address (EA) be the sum (RA|0)+ D.
 128 RS[48:63] are stored into the halfword in storage
 129 addressed by EA.
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Store Halfword Indexed
 136
 137 X-Form
 138
 139 * sthx RS,RA,RB
 140
 141 Pseudo-code:
 142
 143     b <- (RA|0)
 144     EA <- b + (RB)
 145     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 146
 147 Description:
 148
 149 Let the effective address (EA) be the sum
 150 (RA|0)+ (RB). RS[48:63] are stored into the halfword in
 151 storage addressed by EA.
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Store Halfword with Update
 158
 159 D-Form
 160
 161 * sthu RS,D(RA)
 162
 163 Pseudo-code:
 164
 165     EA <- (RA) + EXTS(D)
 166     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 167     RA <- EA
 168
 169 Description:
 170
 171 Let the effective address (EA) be the sum (RA)+ D.
 172 RS[48:63] are stored into the halfword in storage
 173 addressed by EA.
 174
 175 EA is placed into register RA.
 176
 177 If RA=0, the instruction form is invalid.
 178
 179 Special Registers Altered:
 180
 181     None
 182
 183 # Store Halfword with Update Indexed
 184
 185 X-Form
 186
 187 * sthux RS,RA,RB
 188
 189 Pseudo-code:
 190
 191     EA <- (RA) + (RB)
 192     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 193     RA <- EA
 194
 195 Description:
 196
 197 Let the effective address (EA) be the sum (RA)+ (RB).
 198 RS[48:63] are stored into the halfword in storage
 199 addressed by EA.
 200
 201 EA is placed into register RA.
 202
 203 If RA=0, the instruction form is invalid.
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Store Word
 210
 211 D-Form
 212
 213 * stw RS,D(RA)
 214
 215 Pseudo-code:
 216
 217     b <- (RA|0)
 218     EA <- b + EXTS(D)
 219     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 220
 221 Description:
 222
 223 Let the effective address (EA) be the sum (RA|0)+ D.
 224 RS[32:63] are stored into the word in storage addressed
 225 by EA.
 226
 227 Special Registers Altered:
 228
 229     None
 230
 231 # Store Word Indexed
 232
 233 X-Form
 234
 235 * stwx RS,RA,RB
 236
 237 Pseudo-code:
 238
 239     b <- (RA|0)
 240     EA <- b + (RB)
 241     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 242
 243 Description:
 244
 245 Let the effective address (EA) be the sum
 246 (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
 247 age addressed by EA.
 248
 249 Special Registers Altered:
 250
 251     None
 252
 253 # Store Word with Update
 254
 255 D-Form
 256
 257 * stwu RS,D(RA)
 258
 259 Pseudo-code:
 260
 261     EA <- (RA) + EXTS(D)
 262     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 263     RA <- EA
 264
 265 Special Registers Altered:
 266
 267     None
 268
 269 # Store Word with Update Indexed
 270
 271 X-Form
 272
 273 * stwux RS,RA,RB
 274
 275 Pseudo-code:
 276
 277     EA <- (RA) + (RB)
 278     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 279     RA <- EA
 280
 281 Special Registers Altered:
 282
 283     None
 284
 285
 286
 287 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 288
 289 # Store Doubleword
 290
 291 DS-Form
 292
 293 * std RS,DS(RA)
 294
 295 Pseudo-code:
 296
 297     b <- (RA|0)
 298     EA <- b + EXTS(DS || 0b00)
 299     MEM(EA, 8) <- (RS)
 300
 301 Special Registers Altered:
 302
 303     None
 304
 305 # Store Doubleword Indexed
 306
 307 X-Form
 308
 309 * stdx RS,RA,RB
 310
 311 Pseudo-code:
 312
 313     b <- (RA|0)
 314     EA <- b + (RB)
 315     MEM(EA, 8) <- (RS)
 316
 317 Special Registers Altered:
 318
 319     None
 320
 321 # Store Doubleword with Update
 322
 323 DS-Form
 324
 325 * stdu RS,DS(RA)
 326
 327 Pseudo-code:
 328
 329     EA <- (RA) + EXTS(DS || 0b00)
 330     MEM(EA, 8) <- (RS)
 331     RA <- EA
 332
 333 Special Registers Altered:
 334
 335     None
 336
 337 # Store Doubleword with Update Indexed
 338
 339 X-Form
 340
 341 * stdux RS,RA,RB
 342
 343 Pseudo-code:
 344
 345     EA <- (RA) + (RB)
 346     MEM(EA, 8) <- (RS)
 347     RA <- EA
 348
 349 Special Registers Altered:
 350
 351     None
 352
 353
 354 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 355
 356 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
 357 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
 358 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
 359 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
 360 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
 361 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
 362 <!-- byte-reversed into the doubleword addressed by EA. -->
 363
 364
 365 # Store Quadword
 366
 367 DS-Form
 368
 369 * stq RSp,DS(RA)
 370
 371 Pseudo-code:
 372
 373     b <- (RA|0)
 374     EA <- b + EXTS(DS || 0b00)
 375     MEM(EA, 16) <- RSp
 376
 377 Special Registers Altered:
 378
 379     None
 380
 381 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 382
 383 # Store Halfword Byte-Reverse Indexed
 384
 385 X-Form
 386
 387 * sthbrx RS,RA,RB
 388
 389 Pseudo-code:
 390
 391     b <- (RA|0)
 392     EA <- b + (RB)
 393     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 394
 395 Special Registers Altered:
 396
 397     None
 398
 399 # Store Word Byte-Reverse Indexed
 400
 401 X-Form
 402
 403 * stwbrx RS,RA,RB
 404
 405 Pseudo-code:
 406
 407     b <- (RA|0)
 408     EA <- b + (RB)
 409     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 410                    ||(RS)[32:39])
 411
 412 Special Registers Altered:
 413
 414     None
 415
 416 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 417
 418 # Store Doubleword Byte-Reverse Indexed
 419
 420 X-Form
 421
 422 * stdbrx RS,RA,RB
 423
 424 Pseudo-code:
 425
 426     b <- (RA|0)
 427     EA <- b + (RB)
 428     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 429                     || (RS)[40:47] || (RS)[32:39]
 430                     || (RS)[24:31] || (RS)[16:23]
 431                     || (RS)[8:15]  || (RS)[0:7])
 432
 433 Special Registers Altered:
 434
 435     None
 436
 437
 438 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 439
 440 # Store Multiple Word
 441
 442 D-Form
 443
 444 * stmw RS,D(RA)
 445
 446 Pseudo-code:
 447
 448     b <- (RA|0)
 449     EA <- b + EXTS(D)
 450     r <- RS[0:63]
 451     do while r <= 31
 452         MEM(EA, 4) <- GPR(r)[32:63]
 453         r <-  r + 1
 454         EA <-  EA + 4
 455
 456 Special Registers Altered:
 457
 458     None
 459
 460 <!-- Checked March 2021 -->