openpower/isa/fixedstore.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte
  18
  19 D-Form
  20
  21 * stb RS,D(RA)
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + EXTS(D)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31 Let the effective address (EA) be the sum (RA|0)+ D.
  32 RS[56:63] are stored into the byte in storage addressed
  33 by EA.
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Store Byte Indexed
  40
  41 X-Form
  42
  43 * stbx RS,RA,RB
  44
  45 Pseudo-code:
  46
  47     b <- (RA|0)
  48     EA <- b + (RB)
  49     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  50
  51 Description:
  52
  53 Let the effective address (EA) be the sum
  54 (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
  55 age addressed by EA.
  56
  57 Special Registers Altered:
  58
  59     None
  60
  61 # Store Byte with Update
  62
  63 D-Form
  64
  65 * stbu RS,D(RA)
  66
  67 Pseudo-code:
  68
  69     EA <- (RA) + EXTS(D)
  70     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  71     RA <- EA
  72
  73 Special Registers Altered:
  74
  75     None
  76
  77 # Store Byte with Update Indexed
  78
  79 X-Form
  80
  81 * stbux RS,RA,RB
  82
  83 Pseudo-code:
  84
  85     EA <- (RA) + (RB)
  86     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  87     RA <- EA
  88
  89 Special Registers Altered:
  90
  91     None
  92
  93 # Store Halfword
  94
  95 D-Form
  96
  97 * sth RS,D(RA)
  98
  99 Pseudo-code:
 100
 101     b <- (RA|0)
 102     EA <- b + EXTS(D)
 103     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 104
 105 Special Registers Altered:
 106
 107     None
 108
 109 # Store Halfword Indexed
 110
 111 X-Form
 112
 113 * sthx RS,RA,RB
 114
 115 Pseudo-code:
 116
 117     b <- (RA|0)
 118     EA <- b + (RB)
 119     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Store Halfword with Update
 126
 127 D-Form
 128
 129 * sthu RS,D(RA)
 130
 131 Pseudo-code:
 132
 133     EA <- (RA) + EXTS(D)
 134     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 135     RA <- EA
 136
 137 Special Registers Altered:
 138
 139     None
 140
 141 # Store Halfword with Update Indexed
 142
 143 X-Form
 144
 145 * sthux RS,RA,RB
 146
 147 Pseudo-code:
 148
 149     EA <- (RA) + (RB)
 150     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 151     RA <- EA
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Store Word
 158
 159 D-Form
 160
 161 * stw RS,D(RA)
 162
 163 Pseudo-code:
 164
 165     b <- (RA|0)
 166     EA <- b + EXTS(D)
 167     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 168
 169 Special Registers Altered:
 170
 171     None
 172
 173 # Store Word Indexed
 174
 175 X-Form
 176
 177 * stwx RS,RA,RB
 178
 179 Pseudo-code:
 180
 181     b <- (RA|0)
 182     EA <- b + (RB)
 183     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 184
 185 Special Registers Altered:
 186
 187     None
 188
 189 # Store Word with Update
 190
 191 D-Form
 192
 193 * stwu RS,D(RA)
 194
 195 Pseudo-code:
 196
 197     EA <- (RA) + EXTS(D)
 198     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 199     RA <- EA
 200
 201 Special Registers Altered:
 202
 203     None
 204
 205 # Store Word with Update Indexed
 206
 207 X-Form
 208
 209 * stwux RS,RA,RB
 210
 211 Pseudo-code:
 212
 213     EA <- (RA) + (RB)
 214     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 215     RA <- EA
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221
 222
 223 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 224
 225 # Store Doubleword
 226
 227 DS-Form
 228
 229 * std RS,DS(RA)
 230
 231 Pseudo-code:
 232
 233     b <- (RA|0)
 234     EA <- b + EXTS(DS || 0b00)
 235     MEM(EA, 8) <- (RS)
 236
 237 Special Registers Altered:
 238
 239     None
 240
 241 # Store Doubleword Indexed
 242
 243 X-Form
 244
 245 * stdx RS,RA,RB
 246
 247 Pseudo-code:
 248
 249     b <- (RA|0)
 250     EA <- b + (RB)
 251     MEM(EA, 8) <- (RS)
 252
 253 Special Registers Altered:
 254
 255     None
 256
 257 # Store Doubleword with Update
 258
 259 DS-Form
 260
 261 * stdu RS,DS(RA)
 262
 263 Pseudo-code:
 264
 265     EA <- (RA) + EXTS(DS || 0b00)
 266     MEM(EA, 8) <- (RS)
 267     RA <- EA
 268
 269 Special Registers Altered:
 270
 271     None
 272
 273 # Store Doubleword with Update Indexed
 274
 275 X-Form
 276
 277 * stdux RS,RA,RB
 278
 279 Pseudo-code:
 280
 281     EA <- (RA) + (RB)
 282     MEM(EA, 8) <- (RS)
 283     RA <- EA
 284
 285 Special Registers Altered:
 286
 287     None
 288
 289
 290 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 291
 292 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
 293 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
 294 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
 295 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
 296 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
 297 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
 298 <!-- byte-reversed into the doubleword addressed by EA. -->
 299
 300
 301 # Store Quadword
 302
 303 DS-Form
 304
 305 * stq RSp,DS(RA)
 306
 307 Pseudo-code:
 308
 309     b <- (RA|0)
 310     EA <- b + EXTS(DS || 0b00)
 311     MEM(EA, 16) <- RSp
 312
 313 Special Registers Altered:
 314
 315     None
 316
 317 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 318
 319 # Store Halfword Byte-Reverse Indexed
 320
 321 X-Form
 322
 323 * sthbrx RS,RA,RB
 324
 325 Pseudo-code:
 326
 327     b <- (RA|0)
 328     EA <- b + (RB)
 329     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 330
 331 Special Registers Altered:
 332
 333     None
 334
 335 # Store Word Byte-Reverse Indexed
 336
 337 X-Form
 338
 339 * stwbrx RS,RA,RB
 340
 341 Pseudo-code:
 342
 343     b <- (RA|0)
 344     EA <- b + (RB)
 345     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 346                    ||(RS)[32:39])
 347
 348 Special Registers Altered:
 349
 350     None
 351
 352 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 353
 354 # Store Doubleword Byte-Reverse Indexed
 355
 356 X-Form
 357
 358 * stdbrx RS,RA,RB
 359
 360 Pseudo-code:
 361
 362     b <- (RA|0)
 363     EA <- b + (RB)
 364     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 365                     || (RS)[40:47] || (RS)[32:39]
 366                     || (RS)[24:31] || (RS)[16:23]
 367                     || (RS)[8:15]  || (RS)[0:7])
 368
 369 Special Registers Altered:
 370
 371     None
 372
 373
 374 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 375
 376 # Store Multiple Word
 377
 378 D-Form
 379
 380 * stmw RS,D(RA)
 381
 382 Pseudo-code:
 383
 384     b <- (RA|0)
 385     EA <- b + EXTS(D)
 386     r <- RS[0:63]
 387     do while r <= 31
 388         MEM(EA, 4) <- GPR(r)[32:63]
 389         r <-  r + 1
 390         EA <-  EA + 4
 391
 392 Special Registers Altered:
 393
 394     None
 395
 396 <!-- Checked March 2021 -->