openpower/isa/fixedstore.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte
  18
  19 D-Form
  20
  21 * stb RS,D(RA)
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + EXTS(D)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31 Let the effective address (EA) be the sum (RA|0)+ D.
  32 RS[56:63] are stored into the byte in storage addressed
  33 by EA.
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Store Byte Indexed
  40
  41 X-Form
  42
  43 * stbx RS,RA,RB
  44
  45 Pseudo-code:
  46
  47     b <- (RA|0)
  48     EA <- b + (RB)
  49     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  50
  51 Description:
  52
  53 Let the effective address (EA) be the sum
  54 (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
  55 age addressed by EA.
  56
  57 Special Registers Altered:
  58
  59     None
  60
  61 # Store Byte with Update
  62
  63 D-Form
  64
  65 * stbu RS,D(RA)
  66
  67 Pseudo-code:
  68
  69     EA <- (RA) + EXTS(D)
  70     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  71     RA <- EA
  72
  73 Description:
  74
  75 Let the effective address (EA) be the sum (RA)+ D.
  76 RS[56:63] are stored into the byte in storage addressed
  77 by EA.
  78
  79 EA is placed into register RA.
  80
  81 If RA=0, the instruction form is invalid.
  82
  83 Special Registers Altered:
  84
  85     None
  86
  87 # Store Byte with Update Indexed
  88
  89 X-Form
  90
  91 * stbux RS,RA,RB
  92
  93 Pseudo-code:
  94
  95     EA <- (RA) + (RB)
  96     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  97     RA <- EA
  98
  99 Description:
 100
 101 Let the effective address (EA) be the sum (RA)+ (RB).
 102 RS[56:63] are stored into the byte in storage addressed
 103 by EA.
 104
 105 EA is placed into register RA.
 106
 107 If RA=0, the instruction form is invalid.
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Store Halfword
 114
 115 D-Form
 116
 117 * sth RS,D(RA)
 118
 119 Pseudo-code:
 120
 121     b <- (RA|0)
 122     EA <- b + EXTS(D)
 123     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 124
 125 Description:
 126
 127 Let the effective address (EA) be the sum (RA|0)+ D.
 128 RS[48:63] are stored into the halfword in storage
 129 addressed by EA.
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Store Halfword Indexed
 136
 137 X-Form
 138
 139 * sthx RS,RA,RB
 140
 141 Pseudo-code:
 142
 143     b <- (RA|0)
 144     EA <- b + (RB)
 145     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 146
 147 Description:
 148
 149 Let the effective address (EA) be the sum
 150 (RA|0)+ (RB). RS[48:63] are stored into the halfword in
 151 storage addressed by EA.
 152
 153 Special Registers Altered:
 154
 155     None
 156
 157 # Store Halfword with Update
 158
 159 D-Form
 160
 161 * sthu RS,D(RA)
 162
 163 Pseudo-code:
 164
 165     EA <- (RA) + EXTS(D)
 166     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 167     RA <- EA
 168
 169 Description:
 170
 171 Let the effective address (EA) be the sum (RA)+ D.
 172 RS[48:63] are stored into the halfword in storage
 173 addressed by EA.
 174
 175 EA is placed into register RA.
 176
 177 If RA=0, the instruction form is invalid.
 178
 179 Special Registers Altered:
 180
 181     None
 182
 183 # Store Halfword with Update Indexed
 184
 185 X-Form
 186
 187 * sthux RS,RA,RB
 188
 189 Pseudo-code:
 190
 191     EA <- (RA) + (RB)
 192     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 193     RA <- EA
 194
 195 Description:
 196
 197 Let the effective address (EA) be the sum (RA)+ (RB).
 198 RS[48:63] are stored into the halfword in storage
 199 addressed by EA.
 200
 201 EA is placed into register RA.
 202
 203 If RA=0, the instruction form is invalid.
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Store Word
 210
 211 D-Form
 212
 213 * stw RS,D(RA)
 214
 215 Pseudo-code:
 216
 217     b <- (RA|0)
 218     EA <- b + EXTS(D)
 219     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 220
 221 Description:
 222
 223 Let the effective address (EA) be the sum (RA|0)+ D.
 224 RS[32:63] are stored into the word in storage addressed
 225 by EA.
 226
 227 Special Registers Altered:
 228
 229     None
 230
 231 # Store Word Indexed
 232
 233 X-Form
 234
 235 * stwx RS,RA,RB
 236
 237 Pseudo-code:
 238
 239     b <- (RA|0)
 240     EA <- b + (RB)
 241     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 242
 243 Special Registers Altered:
 244
 245     None
 246
 247 # Store Word with Update
 248
 249 D-Form
 250
 251 * stwu RS,D(RA)
 252
 253 Pseudo-code:
 254
 255     EA <- (RA) + EXTS(D)
 256     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 257     RA <- EA
 258
 259 Special Registers Altered:
 260
 261     None
 262
 263 # Store Word with Update Indexed
 264
 265 X-Form
 266
 267 * stwux RS,RA,RB
 268
 269 Pseudo-code:
 270
 271     EA <- (RA) + (RB)
 272     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 273     RA <- EA
 274
 275 Special Registers Altered:
 276
 277     None
 278
 279
 280
 281 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 282
 283 # Store Doubleword
 284
 285 DS-Form
 286
 287 * std RS,DS(RA)
 288
 289 Pseudo-code:
 290
 291     b <- (RA|0)
 292     EA <- b + EXTS(DS || 0b00)
 293     MEM(EA, 8) <- (RS)
 294
 295 Special Registers Altered:
 296
 297     None
 298
 299 # Store Doubleword Indexed
 300
 301 X-Form
 302
 303 * stdx RS,RA,RB
 304
 305 Pseudo-code:
 306
 307     b <- (RA|0)
 308     EA <- b + (RB)
 309     MEM(EA, 8) <- (RS)
 310
 311 Special Registers Altered:
 312
 313     None
 314
 315 # Store Doubleword with Update
 316
 317 DS-Form
 318
 319 * stdu RS,DS(RA)
 320
 321 Pseudo-code:
 322
 323     EA <- (RA) + EXTS(DS || 0b00)
 324     MEM(EA, 8) <- (RS)
 325     RA <- EA
 326
 327 Special Registers Altered:
 328
 329     None
 330
 331 # Store Doubleword with Update Indexed
 332
 333 X-Form
 334
 335 * stdux RS,RA,RB
 336
 337 Pseudo-code:
 338
 339     EA <- (RA) + (RB)
 340     MEM(EA, 8) <- (RS)
 341     RA <- EA
 342
 343 Special Registers Altered:
 344
 345     None
 346
 347
 348 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 349
 350 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
 351 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
 352 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
 353 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
 354 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
 355 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
 356 <!-- byte-reversed into the doubleword addressed by EA. -->
 357
 358
 359 # Store Quadword
 360
 361 DS-Form
 362
 363 * stq RSp,DS(RA)
 364
 365 Pseudo-code:
 366
 367     b <- (RA|0)
 368     EA <- b + EXTS(DS || 0b00)
 369     MEM(EA, 16) <- RSp
 370
 371 Special Registers Altered:
 372
 373     None
 374
 375 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 376
 377 # Store Halfword Byte-Reverse Indexed
 378
 379 X-Form
 380
 381 * sthbrx RS,RA,RB
 382
 383 Pseudo-code:
 384
 385     b <- (RA|0)
 386     EA <- b + (RB)
 387     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 388
 389 Special Registers Altered:
 390
 391     None
 392
 393 # Store Word Byte-Reverse Indexed
 394
 395 X-Form
 396
 397 * stwbrx RS,RA,RB
 398
 399 Pseudo-code:
 400
 401     b <- (RA|0)
 402     EA <- b + (RB)
 403     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 404                    ||(RS)[32:39])
 405
 406 Special Registers Altered:
 407
 408     None
 409
 410 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 411
 412 # Store Doubleword Byte-Reverse Indexed
 413
 414 X-Form
 415
 416 * stdbrx RS,RA,RB
 417
 418 Pseudo-code:
 419
 420     b <- (RA|0)
 421     EA <- b + (RB)
 422     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 423                     || (RS)[40:47] || (RS)[32:39]
 424                     || (RS)[24:31] || (RS)[16:23]
 425                     || (RS)[8:15]  || (RS)[0:7])
 426
 427 Special Registers Altered:
 428
 429     None
 430
 431
 432 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 433
 434 # Store Multiple Word
 435
 436 D-Form
 437
 438 * stmw RS,D(RA)
 439
 440 Pseudo-code:
 441
 442     b <- (RA|0)
 443     EA <- b + EXTS(D)
 444     r <- RS[0:63]
 445     do while r <= 31
 446         MEM(EA, 4) <- GPR(r)[32:63]
 447         r <-  r + 1
 448         EA <-  EA + 4
 449
 450 Special Registers Altered:
 451
 452     None
 453
 454 <!-- Checked March 2021 -->