openpower/isa/fixedstore.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte
  18
  19 D-Form
  20
  21 * stb RS,D(RA)
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + EXTS(D)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31 Let the effective address (EA) be the sum (RA|0)+ D.
  32 RS[56:63] are stored into the byte in storage addressed
  33 by EA.
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Store Byte Indexed
  40
  41 X-Form
  42
  43 * stbx RS,RA,RB
  44
  45 Pseudo-code:
  46
  47     b <- (RA|0)
  48     EA <- b + (RB)
  49     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  50
  51 Special Registers Altered:
  52
  53     None
  54
  55 # Store Byte with Update
  56
  57 D-Form
  58
  59 * stbu RS,D(RA)
  60
  61 Pseudo-code:
  62
  63     EA <- (RA) + EXTS(D)
  64     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  65     RA <- EA
  66
  67 Special Registers Altered:
  68
  69     None
  70
  71 # Store Byte with Update Indexed
  72
  73 X-Form
  74
  75 * stbux RS,RA,RB
  76
  77 Pseudo-code:
  78
  79     EA <- (RA) + (RB)
  80     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  81     RA <- EA
  82
  83 Special Registers Altered:
  84
  85     None
  86
  87 # Store Halfword
  88
  89 D-Form
  90
  91 * sth RS,D(RA)
  92
  93 Pseudo-code:
  94
  95     b <- (RA|0)
  96     EA <- b + EXTS(D)
  97     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
  98
  99 Special Registers Altered:
 100
 101     None
 102
 103 # Store Halfword Indexed
 104
 105 X-Form
 106
 107 * sthx RS,RA,RB
 108
 109 Pseudo-code:
 110
 111     b <- (RA|0)
 112     EA <- b + (RB)
 113     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 114
 115 Special Registers Altered:
 116
 117     None
 118
 119 # Store Halfword with Update
 120
 121 D-Form
 122
 123 * sthu RS,D(RA)
 124
 125 Pseudo-code:
 126
 127     EA <- (RA) + EXTS(D)
 128     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 129     RA <- EA
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Store Halfword with Update Indexed
 136
 137 X-Form
 138
 139 * sthux RS,RA,RB
 140
 141 Pseudo-code:
 142
 143     EA <- (RA) + (RB)
 144     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 145     RA <- EA
 146
 147 Special Registers Altered:
 148
 149     None
 150
 151 # Store Word
 152
 153 D-Form
 154
 155 * stw RS,D(RA)
 156
 157 Pseudo-code:
 158
 159     b <- (RA|0)
 160     EA <- b + EXTS(D)
 161     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 162
 163 Special Registers Altered:
 164
 165     None
 166
 167 # Store Word Indexed
 168
 169 X-Form
 170
 171 * stwx RS,RA,RB
 172
 173 Pseudo-code:
 174
 175     b <- (RA|0)
 176     EA <- b + (RB)
 177     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 178
 179 Special Registers Altered:
 180
 181     None
 182
 183 # Store Word with Update
 184
 185 D-Form
 186
 187 * stwu RS,D(RA)
 188
 189 Pseudo-code:
 190
 191     EA <- (RA) + EXTS(D)
 192     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 193     RA <- EA
 194
 195 Special Registers Altered:
 196
 197     None
 198
 199 # Store Word with Update Indexed
 200
 201 X-Form
 202
 203 * stwux RS,RA,RB
 204
 205 Pseudo-code:
 206
 207     EA <- (RA) + (RB)
 208     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 209     RA <- EA
 210
 211 Special Registers Altered:
 212
 213     None
 214
 215
 216
 217 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 218
 219 # Store Doubleword
 220
 221 DS-Form
 222
 223 * std RS,DS(RA)
 224
 225 Pseudo-code:
 226
 227     b <- (RA|0)
 228     EA <- b + EXTS(DS || 0b00)
 229     MEM(EA, 8) <- (RS)
 230
 231 Special Registers Altered:
 232
 233     None
 234
 235 # Store Doubleword Indexed
 236
 237 X-Form
 238
 239 * stdx RS,RA,RB
 240
 241 Pseudo-code:
 242
 243     b <- (RA|0)
 244     EA <- b + (RB)
 245     MEM(EA, 8) <- (RS)
 246
 247 Special Registers Altered:
 248
 249     None
 250
 251 # Store Doubleword with Update
 252
 253 DS-Form
 254
 255 * stdu RS,DS(RA)
 256
 257 Pseudo-code:
 258
 259     EA <- (RA) + EXTS(DS || 0b00)
 260     MEM(EA, 8) <- (RS)
 261     RA <- EA
 262
 263 Special Registers Altered:
 264
 265     None
 266
 267 # Store Doubleword with Update Indexed
 268
 269 X-Form
 270
 271 * stdux RS,RA,RB
 272
 273 Pseudo-code:
 274
 275     EA <- (RA) + (RB)
 276     MEM(EA, 8) <- (RS)
 277     RA <- EA
 278
 279 Special Registers Altered:
 280
 281     None
 282
 283
 284 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 285
 286 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
 287 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
 288 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
 289 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
 290 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
 291 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
 292 <!-- byte-reversed into the doubleword addressed by EA. -->
 293
 294
 295 # Store Quadword
 296
 297 DS-Form
 298
 299 * stq RSp,DS(RA)
 300
 301 Pseudo-code:
 302
 303     b <- (RA|0)
 304     EA <- b + EXTS(DS || 0b00)
 305     MEM(EA, 16) <- RSp
 306
 307 Special Registers Altered:
 308
 309     None
 310
 311 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 312
 313 # Store Halfword Byte-Reverse Indexed
 314
 315 X-Form
 316
 317 * sthbrx RS,RA,RB
 318
 319 Pseudo-code:
 320
 321     b <- (RA|0)
 322     EA <- b + (RB)
 323     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 324
 325 Special Registers Altered:
 326
 327     None
 328
 329 # Store Word Byte-Reverse Indexed
 330
 331 X-Form
 332
 333 * stwbrx RS,RA,RB
 334
 335 Pseudo-code:
 336
 337     b <- (RA|0)
 338     EA <- b + (RB)
 339     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 340                    ||(RS)[32:39])
 341
 342 Special Registers Altered:
 343
 344     None
 345
 346 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 347
 348 # Store Doubleword Byte-Reverse Indexed
 349
 350 X-Form
 351
 352 * stdbrx RS,RA,RB
 353
 354 Pseudo-code:
 355
 356     b <- (RA|0)
 357     EA <- b + (RB)
 358     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 359                     || (RS)[40:47] || (RS)[32:39]
 360                     || (RS)[24:31] || (RS)[16:23]
 361                     || (RS)[8:15]  || (RS)[0:7])
 362
 363 Special Registers Altered:
 364
 365     None
 366
 367
 368 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 369
 370 # Store Multiple Word
 371
 372 D-Form
 373
 374 * stmw RS,D(RA)
 375
 376 Pseudo-code:
 377
 378     b <- (RA|0)
 379     EA <- b + EXTS(D)
 380     r <- RS[0:63]
 381     do while r <= 31
 382         MEM(EA, 4) <- GPR(r)[32:63]
 383         r <-  r + 1
 384         EA <-  EA + 4
 385
 386 Special Registers Altered:
 387
 388     None
 389
 390 <!-- Checked March 2021 -->