1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that store from a register to RAM -->
5 <!-- Note that these pages also define equivalent load instructions, -->
6 <!-- these are described in fixedload.mdwn -->
8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
27 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
31 Let the effective address (EA) be the sum (RA|0)+ D.
32 RS[56:63] are stored into the byte in storage addressed
35 Special Registers Altered:
49 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
53 Let the effective address (EA) be the sum
54 (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
57 Special Registers Altered:
61 # Store Byte with Update
70 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
75 Let the effective address (EA) be the sum (RA)+ D.
76 RS[56:63] are stored into the byte in storage addressed
79 EA is placed into register RA.
81 If RA=0, the instruction form is invalid.
83 Special Registers Altered:
87 # Store Byte with Update Indexed
96 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
101 Let the effective address (EA) be the sum (RA)+ (RB).
102 RS[56:63] are stored into the byte in storage addressed
105 EA is placed into register RA.
107 If RA=0, the instruction form is invalid.
109 Special Registers Altered:
123 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
127 Let the effective address (EA) be the sum (RA|0)+ D.
128 RS[48:63] are stored into the halfword in storage
131 Special Registers Altered:
135 # Store Halfword Indexed
145 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
149 Let the effective address (EA) be the sum
150 (RA|0)+ (RB). RS[48:63] are stored into the halfword in
151 storage addressed by EA.
153 Special Registers Altered:
157 # Store Halfword with Update
166 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
171 Let the effective address (EA) be the sum (RA)+ D.
172 RS[48:63] are stored into the halfword in storage
175 EA is placed into register RA.
177 If RA=0, the instruction form is invalid.
179 Special Registers Altered:
183 # Store Halfword with Update Indexed
192 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
197 Let the effective address (EA) be the sum (RA)+ (RB).
198 RS[48:63] are stored into the halfword in storage
201 EA is placed into register RA.
203 If RA=0, the instruction form is invalid.
205 Special Registers Altered:
219 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
223 Let the effective address (EA) be the sum (RA|0)+ D.
224 RS[32:63] are stored into the word in storage addressed
227 Special Registers Altered:
241 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
245 Let the effective address (EA) be the sum
246 (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
249 Special Registers Altered:
253 # Store Word with Update
262 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
267 Let the effective address (EA) be the sum (RA)+ D.
268 RS[32:63] are stored into the word in storage addressed
271 EA is placed into register RA.
273 If RA=0, the instruction form is invalid.
275 Special Registers Altered:
279 # Store Word with Update Indexed
288 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
293 Let the effective address (EA) be the sum (RA)+ (RB).
294 RS[32:63] are stored into the word in storage addressed
297 EA is placed into register RA.
299 If RA=0, the instruction form is invalid.
301 Special Registers Altered:
307 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
318 EA <- b + EXTS(DS || 0b00)
321 Special Registers Altered:
325 # Store Doubleword Indexed
337 Special Registers Altered:
341 # Store Doubleword with Update
349 EA <- (RA) + EXTS(DS || 0b00)
353 Special Registers Altered:
357 # Store Doubleword with Update Indexed
369 Special Registers Altered:
374 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
376 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
377 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
378 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
379 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
380 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
381 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
382 <!-- byte-reversed into the doubleword addressed by EA. -->
394 EA <- b + EXTS(DS || 0b00)
397 Special Registers Altered:
401 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
403 # Store Halfword Byte-Reverse Indexed
413 MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
415 Special Registers Altered:
419 # Store Word Byte-Reverse Indexed
429 MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
432 Special Registers Altered:
436 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
438 # Store Doubleword Byte-Reverse Indexed
448 MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
449 || (RS)[40:47] || (RS)[32:39]
450 || (RS)[24:31] || (RS)[16:23]
451 || (RS)[8:15] || (RS)[0:7])
453 Special Registers Altered:
458 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
460 # Store Multiple Word
472 MEM(EA, 4) <- GPR(r)[32:63]
476 Special Registers Altered:
480 <!-- Checked March 2021 -->