openpower/isa/fixedstore.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte
  18
  19 D-Form
  20
  21 * stb RS,D(RA)
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + EXTS(D)
  27     MEM(EA, 1) <- (RS)[56:63]
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Byte Indexed
  34
  35 X-Form
  36
  37 * stbx RS,RA,RB
  38
  39 Pseudo-code:
  40
  41     b <- (RA|0)
  42     EA <- b + (RB)
  43     MEM(EA, 1) <- (RS)[56:63]
  44
  45 Special Registers Altered:
  46
  47     None
  48
  49 # Store Byte with Update
  50
  51 D-Form
  52
  53 * stbu RS,D(RA)
  54
  55 Pseudo-code:
  56
  57     EA <- (RA) + EXTS(D)
  58     MEM(EA, 1) <- (RS)[56:63]
  59     RA <- EA
  60
  61 Special Registers Altered:
  62
  63     None
  64
  65 # Store Byte with Update Indexed
  66
  67 X-Form
  68
  69 * stbux RS,RA,RB
  70
  71 Pseudo-code:
  72
  73     EA <- (RA) + (RB)
  74     MEM(EA, 1) <- (RS)[56:63]
  75     RA <- EA
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Store Halfword
  82
  83 D-Form
  84
  85 * sth RS,D(RA)
  86
  87 Pseudo-code:
  88
  89     b <- (RA|0)
  90     EA <- b + EXTS(D)
  91     MEM(EA, 2) <- (RS)[48:63]
  92
  93 Special Registers Altered:
  94
  95     None
  96
  97 # Store Halfword Indexed
  98
  99 X-Form
 100
 101 * sthx RS,RA,RB
 102
 103 Pseudo-code:
 104
 105     b <- (RA|0)
 106     EA <- b + (RB)
 107     MEM(EA, 2) <- (RS)[48:63]
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Store Halfword with Update
 114
 115 D-Form
 116
 117 * sthu RS,D(RA)
 118
 119 Pseudo-code:
 120
 121     EA <- (RA) + EXTS(D)
 122     MEM(EA, 2) <- (RS)[48:63]
 123     RA <- EA
 124
 125 Special Registers Altered:
 126
 127     None
 128
 129 # Store Halfword with Update Indexed
 130
 131 X-Form
 132
 133 * sthux RS,RA,RB
 134
 135 Pseudo-code:
 136
 137     EA <- (RA) + (RB)
 138     MEM(EA, 2) <- (RS)[48:63]
 139     RA <- EA
 140
 141 Special Registers Altered:
 142
 143     None
 144
 145 # Store Word
 146
 147 D-Form
 148
 149 * stw RS,D(RA)
 150
 151 Pseudo-code:
 152
 153     b <- (RA|0)
 154     EA <- b + EXTS(D)
 155     MEM(EA, 4) <- (RS)[32:63]
 156
 157 Special Registers Altered:
 158
 159     None
 160
 161 # Store Word Indexed
 162
 163 X-Form
 164
 165 * stwx RS,RA,RB
 166
 167 Pseudo-code:
 168
 169     b <- (RA|0)
 170     EA <- b + (RB)
 171     MEM(EA, 4) <- (RS)[32:63]
 172
 173 Special Registers Altered:
 174
 175     None
 176
 177 # Store Word with Update
 178
 179 D-Form
 180
 181 * stwu RS,D(RA)
 182
 183 Pseudo-code:
 184
 185     EA <- (RA) + EXTS(D)
 186     MEM(EA, 4) <- (RS)[32:63]
 187     RA <- EA
 188
 189 Special Registers Altered:
 190
 191     None
 192
 193 # Store Word with Update Indexed
 194
 195 X-Form
 196
 197 * stwux RS,RA,RB
 198
 199 Pseudo-code:
 200
 201     EA <- (RA) + (RB)
 202     MEM(EA, 4) <- (RS)[32:63]
 203     RA <- EA
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209
 210
 211 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 212
 213 # Store Doubleword
 214
 215 DS-Form
 216
 217 * std RS,DS(RA)
 218
 219 Pseudo-code:
 220
 221     b <- (RA|0)
 222     EA <- b + EXTS(DS || 0b00)
 223     MEM(EA, 8) <- (RS)
 224
 225 Special Registers Altered:
 226
 227     None
 228
 229 # Store Doubleword Indexed
 230
 231 X-Form
 232
 233 * stdx RS,RA,RB
 234
 235 Pseudo-code:
 236
 237     b <- (RA|0)
 238     EA <- b + (RB)
 239     MEM(EA, 8) <- (RS)
 240
 241 Special Registers Altered:
 242
 243     None
 244
 245 # Store Doubleword with Update
 246
 247 DS-Form
 248
 249 * stdu RS,DS(RA)
 250
 251 Pseudo-code:
 252
 253     EA <- (RA) + EXTS(DS || 0b00)
 254     MEM(EA, 8) <- (RS)
 255     RA <- EA
 256
 257 Special Registers Altered:
 258
 259     None
 260
 261 # Store Doubleword with Update Indexed
 262
 263 X-Form
 264
 265 * stdux RS,RA,RB
 266
 267 Pseudo-code:
 268
 269     EA <- (RA) + (RB)
 270     MEM(EA, 8) <- (RS)
 271     RA <- EA
 272
 273 Special Registers Altered:
 274
 275     None
 276
 277
 278 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
 279
 280 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
 281 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
 282 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
 283 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
 284 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
 285 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
 286 <!-- byte-reversed into the doubleword addressed by EA. -->
 287
 288
 289 # Store Quadword
 290
 291 DS-Form
 292
 293 * stq RSp,DS(RA)
 294
 295 Pseudo-code:
 296
 297     b <- (RA|0)
 298     EA <- b + EXTS(DS || 0b00)
 299     MEM(EA, 16) <- RSp
 300
 301 Special Registers Altered:
 302
 303     None
 304
 305 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 306
 307 # Store Halfword Byte-Reverse Indexed
 308
 309 X-Form
 310
 311 * sthbrx RS,RA,RB
 312
 313 Pseudo-code:
 314
 315     b <- (RA|0)
 316     EA <- b + (RB)
 317     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 318
 319 Special Registers Altered:
 320
 321     None
 322
 323 # Store Word Byte-Reverse Indexed
 324
 325 X-Form
 326
 327 * stwbrx RS,RA,RB
 328
 329 Pseudo-code:
 330
 331     b <- (RA|0)
 332     EA <- b + (RB)
 333     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 334                    ||(RS)[32:39])
 335
 336 Special Registers Altered:
 337
 338     None
 339
 340 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 341
 342 # Store Doubleword Byte-Reverse Indexed
 343
 344 X-Form
 345
 346 * stdbrx RS,RA,RB
 347
 348 Pseudo-code:
 349
 350     b <- (RA|0)
 351     EA <- b + (RB)
 352     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 353                     || (RS)[40:47] || (RS)[32:39]
 354                     || (RS)[24:31] || (RS)[16:23]
 355                     || (RS)[8:15]  || (RS)[0:7])
 356
 357 Special Registers Altered:
 358
 359     None
 360
 361
 362 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 363
 364 # Store Multiple Word
 365
 366 D-Form
 367
 368 * stmw RS,D(RA)
 369
 370 Pseudo-code:
 371
 372     b <- (RA|0)
 373     EA <- b + EXTS(D)
 374     r <- RS[0:63]
 375     do while r <= 31
 376         MEM(EA, 4) <- GPR(r)[32:63]
 377         r <-  r + 1
 378         EA <-  EA + 4
 379
 380 Special Registers Altered:
 381
 382     None
 383
 384 <!-- Checked March 2021 -->