openpower/isa/fixedstoreshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte Shifted Indexed
  18
  19 X-Form
  20
  21 * stbsx RS,RA,RB,SH
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + (RB) << (SH+1)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31     Let the effective address (EA) be the sum of the contents of
  32     register RB shifted by (SH+1), and (RA|0).
  33
  34     RS [56:63] are stored into the byte in storage addressed by EA.
  35
  36 Special Registers Altered:
  37
  38     None
  39
  40 # Store Byte Shifted with Update Indexed
  41
  42 X-Form
  43
  44 * stbsux RS,RA,RB,SH
  45
  46 Pseudo-code:
  47
  48     EA <- (RA) + (RB) << (SH+1)
  49     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  50     RA <- EA
  51
  52 Description:
  53
  54     Let the effective address (EA) be the sum of the contents of
  55     register RB shifted by (SH+1), and (RA).
  56
  57     RS[56:63] are stored into the byte in storage addressed by EA.
  58
  59     EA is placed into register RA.
  60
  61     If RA=0, the instruction form is invalid.
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Store Halfword Shifted Indexed
  68
  69 X-Form
  70
  71 * sthsx RS,RA,RB,SH
  72
  73 Pseudo-code:
  74
  75     b <- (RA|0)
  76     EA <- b + (RB) << (SH+1)
  77     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
  78
  79 Description:
  80
  81     Let the effective address (EA) be the sum of the contents of
  82     register RB shifted by (SH+1), and (RA|0).
  83
  84     RS[48:63] are stored into the halfword in storage addressed by EA.
  85
  86 Special Registers Altered:
  87
  88     None
  89
  90 # Store Halfword Shifted with Update Indexed
  91
  92 X-Form
  93
  94 * sthsux RS,RA,RB,SH
  95
  96 Pseudo-code:
  97
  98     EA <- (RA) + (RB) << (SH+1)
  99     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
 100     RA <- EA
 101
 102 Description:
 103
 104     Let the effective address (EA) be the sum of the contents of
 105     register RB shifted by (SH+1), and (RA).
 106
 107     RS[48:63] are stored into the halfword in storage addressed by EA.
 108
 109     EA is placed into register RA.
 110
 111     If RA=0, the instruction form is invalid.
 112
 113 Special Registers Altered:
 114
 115     None
 116
 117 # Store Word Shifted Indexed
 118
 119 X-Form
 120
 121 * stwsx RS,RA,RB,SH
 122
 123 Pseudo-code:
 124
 125     b <- (RA|0)
 126     EA <- b + (RB) << (SH+1)
 127     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 128
 129 Description:
 130
 131     Let the effective address (EA) be the sum of the contents of
 132     register RB shifted by (SH+1), and (RA|0).
 133
 134     RS[32:63] are stored into the word in storage addressed by EA.
 135
 136 Special Registers Altered:
 137
 138     None
 139
 140 # Store Word Shifted with Update Indexed
 141
 142 X-Form
 143
 144 * stwsux RS,RA,RB,SH
 145
 146 Pseudo-code:
 147
 148     EA <- (RA) + (RB) << (SH+1)
 149     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 150     RA <- EA
 151
 152 Description:
 153
 154     Let the effective address (EA) be the sum of the contents of
 155     register RB shifted by (SH+1), and (RA).
 156
 157     RS[32:63] are stored into the word in storage addressed by EA.
 158
 159     EA is placed into register RA.
 160
 161     If RA=0, the instruction form is invalid.
 162
 163 Special Registers Altered:
 164
 165     None
 166
 167
 168
 169 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 170
 171 # Store Doubleword Shifted Indexed
 172
 173 X-Form
 174
 175 * stdsx RS,RA,RB,SH
 176
 177 Pseudo-code:
 178
 179     b <- (RA|0)
 180     EA <- b + (RB) << (SH+1)
 181     MEM(EA, 8) <- (RS)
 182
 183 Description:
 184
 185     Let the effective address (EA) be the sum of the contents of
 186     register RB shifted by (SH+1), and (RA|0).
 187
 188     (RS) is stored into the doubleword in storage addressed by EA.
 189
 190 Special Registers Altered:
 191
 192     None
 193
 194 # Store Doubleword Shifted with Update Indexed
 195
 196 X-Form
 197
 198 * stdsux RS,RA,RB,SH
 199
 200 Pseudo-code:
 201
 202     EA <- (RA) + (RB) << (SH+1)
 203     MEM(EA, 8) <- (RS)
 204     RA <- EA
 205
 206 Description:
 207
 208     Let the effective address (EA) be the sum of the contents of
 209     register (RB) shifted by (SH+1), and (RA).
 210
 211     (RS) is stored into the doubleword in storage addressed by EA.
 212
 213     EA is placed into register RA.
 214
 215     If RA=0, the instruction form is invalid.
 216
 217 Special Registers Altered:
 218
 219     None
 220
 221
 222 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 223
 224 # Store Halfword Byte-Reverse Shifted Indexed
 225
 226 X-Form
 227
 228 * sthbrsx RS,RA,RB,SH
 229
 230 Pseudo-code:
 231
 232     b <- (RA|0)
 233     EA <- b + (RB) << (SH+1)
 234     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 235
 236 Description:
 237
 238     Let the effective address (EA) be the sum of the contents of
 239     register RB shifted by (SH+1), and (RA|0).
 240
 241     (RS)56:63 are stored into bits 0:7 of the halfword in storage
 242     addressed by EA.  (RS)[48:55] are stored into bits 8:15 of
 243     the halfword in storage addressed by EA.
 244
 245 Special Registers Altered:
 246
 247     None
 248
 249 # Store Word Byte-Reverse Shifted Indexed
 250
 251 X-Form
 252
 253 * stwbrsx RS,RA,RB,SH
 254
 255 Pseudo-code:
 256
 257     b <- (RA|0)
 258     EA <- b + (RB) << (SH+1)
 259     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 260                    ||(RS)[32:39])
 261
 262 Description:
 263
 264     Let the effective address (EA) be the sum of the contents of
 265     register RB shifted by (SH+1), and (RA|0).
 266
 267     (RS)[56:63] are stored into bits 0:7 of the
 268     word in storage addressed by EA. (RS) [48:55] are stored
 269     into bits 8:15 of the word in storage addressed by EA.
 270     (RS)[40:47] are stored into bits 16:23 of the word in stor-
 271     age addressed by EA. (RS) [32:39] are stored into bits
 272     24:31 of the word in storage addressed by EA.
 273
 274 Special Registers Altered:
 275
 276     None
 277
 278 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 279
 280 # Store Doubleword Byte-Reverse Shifted Indexed
 281
 282 X-Form
 283
 284 * stdbrsx RS,RA,RB,SH
 285
 286 Pseudo-code:
 287
 288     b <- (RA|0)
 289     EA <- b + (RB) << (SH+1)
 290     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 291                     || (RS)[40:47] || (RS)[32:39]
 292                     || (RS)[24:31] || (RS)[16:23]
 293                     || (RS)[8:15]  || (RS)[0:7])
 294
 295 Description:
 296
 297     Let the effective address (EA) be the sum of the contents of
 298     register RB shifted by (SH+1), and (RA|0).
 299
 300     (RS)[56:63] are stored into bits 0:7 of the
 301     doubleword in storage addressed by EA. (RS)[48:55] are
 302     stored into bits 8:15 of the doubleword in storage
 303     addressed by EA. (RS) [40:47] are stored into bits 16:23 of
 304     the doubleword in storage addressed by EA. (RS)[32:39]
 305     are stored into bits 23:31 of the doubleword in storage
 306     addressed by EA. (RS) [24:31] are stored into bits 32:39 of
 307     the doubleword in storage addressed by EA. (RS)[16:23]
 308     are stored into bits 40:47 of the doubleword in storage
 309     addressed by EA. (RS)[8:15] are stored into bits 48:55 of
 310     the doubleword in storage addressed by EA. (RS)[0:7]
 311     are stored into bits 56:63 of the doubleword in storage
 312     addressed by EA.
 313
 314 Special Registers Altered:
 315
 316     None
 317
 318 <!-- Checked March 2021 -->