1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that store from a register to RAM -->
5 <!-- Note that these pages also define equivalent load instructions, -->
6 <!-- these are described in fixedload.mdwn -->
8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
17 # Store Byte Shifted Indexed
26 EA <- b + (RB) << (SH+1)
27 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
31 Let the effective address (EA) be the sum of the contents of
32 register RB shifted by (SH+1), and (RA|0).
34 RS [56:63] are stored into the byte in storage addressed by EA.
36 Special Registers Altered:
40 # Store Byte Shifted with Update Indexed
48 EA <- (RA) + (RB) << (SH+1)
49 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
54 Let the effective address (EA) be the sum of the contents of
55 register RB shifted by (SH+1), and (RA).
57 RS[56:63] are stored into the byte in storage addressed by EA.
59 EA is placed into register RA.
61 If RA=0, the instruction form is invalid.
63 Special Registers Altered:
67 # Store Halfword Shifted Indexed
76 EA <- b + (RB) << (SH+1)
77 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
81 Let the effective address (EA) be the sum of the contents of
82 register RB shifted by (SH+1), and (RA|0).
84 RS[48:63] are stored into the halfword in storage addressed by EA.
86 Special Registers Altered:
90 # Store Halfword Shifted with Update Indexed
98 EA <- (RA) + (RB) << (SH+1)
99 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
104 Let the effective address (EA) be the sum of the contents of
105 register RB shifted by (SH+1), and (RA).
107 RS[48:63] are stored into the halfword in storage addressed by EA.
109 EA is placed into register RA.
111 If RA=0, the instruction form is invalid.
113 Special Registers Altered:
117 # Store Word Shifted Indexed
126 EA <- b + (RB) << (SH+1)
127 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
131 Let the effective address (EA) be the sum of the contents of
132 register RB shifted by (SH+1), and (RA|0).
134 RS[32:63] are stored into the word in storage addressed by EA.
136 Special Registers Altered:
140 # Store Word Shifted with Update Indexed
148 EA <- (RA) + (RB) << (SH+1)
149 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
154 Let the effective address (EA) be the sum of the contents of
155 register RB shifted by (SH+1), and (RA).
157 RS[32:63] are stored into the word in storage addressed by EA.
159 EA is placed into register RA.
161 If RA=0, the instruction form is invalid.
163 Special Registers Altered:
169 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
171 # Store Doubleword Shifted Indexed
180 EA <- b + (RB) << (SH+1)
185 Let the effective address (EA) be the sum of the contents of
186 register RB shifted by (SH+1), and (RA|0).
188 (RS) is stored into the doubleword in storage addressed by EA.
190 Special Registers Altered:
194 # Store Doubleword Shifted with Update Indexed
202 EA <- (RA) + (RB) << (SH+1)
208 Let the effective address (EA) be the sum of the contents of
209 register (RB) shifted by (SH+1), and (RA).
211 (RS) is stored into the doubleword in storage addressed by EA.
213 EA is placed into register RA.
215 If RA=0, the instruction form is invalid.
217 Special Registers Altered:
222 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
224 # Store Halfword Byte-Reverse Shifted Indexed
228 * sthbrsx RS,RA,RB,SH
233 EA <- b + (RB) << (SH+1)
234 MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
238 Let the effective address (EA) be the sum of the contents of
239 register RB shifted by (SH+1), and (RA|0).
241 (RS)56:63 are stored into bits 0:7 of the halfword in storage
242 addressed by EA. (RS)[48:55] are stored into bits 8:15 of
243 the halfword in storage addressed by EA.
245 Special Registers Altered:
249 # Store Word Byte-Reverse Shifted Indexed
253 * stwbrsx RS,RA,RB,SH
258 EA <- b + (RB) << (SH+1)
259 MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
264 Let the effective address (EA) be the sum of the contents of
265 register RB shifted by (SH+1), and (RA|0).
267 (RS)[56:63] are stored into bits 0:7 of the
268 word in storage addressed by EA. (RS) [48:55] are stored
269 into bits 8:15 of the word in storage addressed by EA.
270 (RS)[40:47] are stored into bits 16:23 of the word in stor-
271 age addressed by EA. (RS) [32:39] are stored into bits
272 24:31 of the word in storage addressed by EA.
274 Special Registers Altered:
278 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
280 # Store Doubleword Byte-Reverse Shifted Indexed
284 * stdbrsx RS,RA,RB,SH
289 EA <- b + (RB) << (SH+1)
290 MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
291 || (RS)[40:47] || (RS)[32:39]
292 || (RS)[24:31] || (RS)[16:23]
293 || (RS)[8:15] || (RS)[0:7])
297 Let the effective address (EA) be the sum of the contents of
298 register RB shifted by (SH+1), and (RA|0).
300 (RS)[56:63] are stored into bits 0:7 of the
301 doubleword in storage addressed by EA. (RS)[48:55] are
302 stored into bits 8:15 of the doubleword in storage
303 addressed by EA. (RS) [40:47] are stored into bits 16:23 of
304 the doubleword in storage addressed by EA. (RS)[32:39]
305 are stored into bits 23:31 of the doubleword in storage
306 addressed by EA. (RS) [24:31] are stored into bits 32:39 of
307 the doubleword in storage addressed by EA. (RS)[16:23]
308 are stored into bits 40:47 of the doubleword in storage
309 addressed by EA. (RS)[8:15] are stored into bits 48:55 of
310 the doubleword in storage addressed by EA. (RS)[0:7]
311 are stored into bits 56:63 of the doubleword in storage
314 Special Registers Altered:
318 <!-- Checked March 2021 -->