1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that store from a register to RAM -->
5 <!-- Note that these pages also define equivalent load instructions, -->
6 <!-- these are described in fixedload.mdwn -->
8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
17 # Store Byte Shifted Indexed
26 EA <- b + (RB) << (SH+1)
27 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
31 Let the effective address (EA) be the sum of the contents of
32 register RB shifted by (SH+1) and (RA|0).
33 RS [56:63] are stored into the byte in storage addressed by EA.
35 Special Registers Altered:
39 # Store Byte Shifted with Update Indexed
47 EA <- (RA) + (RB) << (SH+1)
48 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
53 Let the effective address (EA) be the sum of the contents of
54 register RB shifted by (SH+1) and (RA).
55 RS[56:63] are stored into the byte in storage addressed
58 EA is placed into register RA.
60 If RA=0, the instruction form is invalid.
62 Special Registers Altered:
66 # Store Halfword Shifted Indexed
75 EA <- b + (RB) << (SH+1)
76 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
80 Let the effective address (EA) be the sum of the contents of
81 register RB shifted by (SH+1) and (RA|0).
82 RS[48:63] are stored into the halfword in
83 storage addressed by EA.
85 Special Registers Altered:
89 # Store Halfword Shifted with Update Indexed
97 EA <- (RA) + (RB) << (SH+1)
98 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
103 Let the effective address (EA) be the sum of the contents of
104 register RB shifted by (SH+1) and (RB).
105 RS[48:63] are stored into the halfword in storage
108 EA is placed into register RA.
110 If RA=0, the instruction form is invalid.
112 Special Registers Altered:
116 # Store Word Shifted Indexed
125 EA <- b + (RB) << (SH+1)
126 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
130 Let the effective address (EA) be the sum of the contents of
131 register RB shifted by (SH+1) and (RA|0).
132 RS[32:63] are stored into the word in stor-
135 Special Registers Altered:
139 # Store Word Shifted with Update Indexed
147 EA <- (RA) + (RB) << (SH+1)
148 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
153 Let the effective address (EA) be the sum (RA)+ (RB).
154 RS[32:63] are stored into the word in storage addressed
157 EA is placed into register RA.
159 If RA=0, the instruction form is invalid.
161 Special Registers Altered:
167 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
169 # Store Doubleword Shifted Indexed
178 EA <- b + (RB) << (SH+1)
183 Let the effective address (EA) be the sum
184 (RA|0)+ (RB). (RS) is stored into the doubleword in
185 storage addressed by EA.
187 Special Registers Altered:
191 # Store Doubleword Shifted with Update Indexed
199 EA <- (RA) + (RB) << (SH+1)
205 Let the effective address (EA) be the sum (RA)+ (RB).
206 (RS) is stored into the doubleword in storage
209 EA is placed into register RA.
211 If RA=0, the instruction form is invalid.
213 Special Registers Altered:
218 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
220 # Store Halfword Byte-Reverse Shifted Indexed
224 * sthbrsx RS,RA,RB,SH
229 EA <- b + (RB) << (SH+1)
230 MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
234 Let the effective address (EA) be the sum
235 (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
236 halfword in storage addressed by EA. (RS) 48:55 are
237 stored into bits 8:15 of the halfword in storage
240 Special Registers Altered:
244 # Store Word Byte-Reverse Shifted Indexed
248 * stwbrsx RS,RA,RB,SH
253 EA <- b + (RB) << (SH+1)
254 MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
259 Let the effective address (EA) be the sum
260 (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
261 word in storage addressed by EA. (RS) [48:55] are stored
262 into bits 8:15 of the word in storage addressed by EA.
263 (RS)[40:47] are stored into bits 16:23 of the word in stor-
264 age addressed by EA. (RS) [32:39] are stored into bits
265 24:31 of the word in storage addressed by EA.
267 Special Registers Altered:
271 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
273 # Store Doubleword Byte-Reverse Shifted Indexed
277 * stdbrsx RS,RA,RB,SH
282 EA <- b + (RB) << (SH+1)
283 MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
284 || (RS)[40:47] || (RS)[32:39]
285 || (RS)[24:31] || (RS)[16:23]
286 || (RS)[8:15] || (RS)[0:7])
290 Let the effective address (EA) be the sum
291 (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
292 doubleword in storage addressed by EA. (RS) [48:55] are
293 stored into bits 8:15 of the doubleword in storage
294 addressed by EA. (RS) [40:47] are stored into bits 16:23 of
295 the doubleword in storage addressed by EA. (RS) [32:39]
296 are stored into bits 23:31 of the doubleword in storage
297 addressed by EA. (RS) [24:31] are stored into bits 32:39 of
298 the doubleword in storage addressed by EA. (RS) [16:23]
299 are stored into bits 40:47 of the doubleword in storage
300 addressed by EA. (RS)[8:15] are stored into bits 48:55 of
301 the doubleword in storage addressed by EA. (RS) [0:7]
302 are stored into bits 56:63 of the doubleword in storage
305 Special Registers Altered:
309 <!-- Checked March 2021 -->