openpower/isa/fixedstoreshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte Shifted Indexed
  18
  19 X-Form
  20
  21 * stbsx RS,RA,RB,SH
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + (RB) << (SH+1)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31     Let the effective address (EA) be the sum of the contents of
  32     register RB shifted by (SH+1) and (RA|0).
  33     RS [56:63] are stored into the byte in storage addressed by EA.
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Store Byte Shifted with Update Indexed
  40
  41 X-Form
  42
  43 * stbsux RS,RA,RB,SH
  44
  45 Pseudo-code:
  46
  47     EA <- (RA) + (RB) << (SH+1)
  48     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  49     RA <- EA
  50
  51 Description:
  52
  53     Let the effective address (EA) be the sum of the contents of
  54     register RB shifted by (SH+1) and (RA).
  55     RS[56:63] are stored into the byte in storage addressed
  56     by EA.
  57
  58     EA is placed into register RA.
  59
  60     If RA=0, the instruction form is invalid.
  61
  62 Special Registers Altered:
  63
  64     None
  65
  66 # Store Halfword Shifted Indexed
  67
  68 X-Form
  69
  70 * sthsx RS,RA,RB,SH
  71
  72 Pseudo-code:
  73
  74     b <- (RA|0)
  75     EA <- b + (RB) << (SH+1)
  76     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
  77
  78 Description:
  79
  80     Let the effective address (EA) be the sum of the contents of
  81     register RB shifted by (SH+1) and (RA|0).
  82     RS[48:63] are stored into the halfword in
  83     storage addressed by EA.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Store Halfword Shifted with Update Indexed
  90
  91 X-Form
  92
  93 * sthsux RS,RA,RB,SH
  94
  95 Pseudo-code:
  96
  97     EA <- (RA) + (RB) << (SH+1)
  98     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
  99     RA <- EA
 100
 101 Description:
 102
 103     Let the effective address (EA) be the sum of the contents of
 104     register RB shifted by (SH+1) and (RB).
 105     RS[48:63] are stored into the halfword in storage
 106     addressed by EA.
 107
 108     EA is placed into register RA.
 109
 110     If RA=0, the instruction form is invalid.
 111
 112 Special Registers Altered:
 113
 114     None
 115
 116 # Store Word Shifted Indexed
 117
 118 X-Form
 119
 120 * stwsx RS,RA,RB,SH
 121
 122 Pseudo-code:
 123
 124     b <- (RA|0)
 125     EA <- b + (RB) << (SH+1)
 126     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 127
 128 Description:
 129
 130     Let the effective address (EA) be the sum of the contents of
 131     register RB shifted by (SH+1) and (RA|0).
 132     RS[32:63] are stored into the word in storage
 133     addressed by EA.
 134
 135 Special Registers Altered:
 136
 137     None
 138
 139 # Store Word Shifted with Update Indexed
 140
 141 X-Form
 142
 143 * stwsux RS,RA,RB,SH
 144
 145 Pseudo-code:
 146
 147     EA <- (RA) + (RB) << (SH+1)
 148     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 149     RA <- EA
 150
 151 Description:
 152
 153     Let the effective address (EA) be the sum of the contents of
 154     register RB shifted by (SH+1) and (RB).
 155     RS[32:63] are stored into the word in storage addressed
 156     by EA.
 157
 158     EA is placed into register RA.
 159
 160     If RA=0, the instruction form is invalid.
 161
 162 Special Registers Altered:
 163
 164     None
 165
 166
 167
 168 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 169
 170 # Store Doubleword Shifted Indexed
 171
 172 X-Form
 173
 174 * stdsx RS,RA,RB,SH
 175
 176 Pseudo-code:
 177
 178     b <- (RA|0)
 179     EA <- b + (RB) << (SH+1)
 180     MEM(EA, 8) <- (RS)
 181
 182 Description:
 183
 184     Let the effective address (EA) be the sum of the contents of
 185     register RB shifted by (SH+1) and (RA|0).
 186     (RS) is stored into the doubleword in
 187     storage addressed by EA.
 188
 189 Special Registers Altered:
 190
 191     None
 192
 193 # Store Doubleword Shifted with Update Indexed
 194
 195 X-Form
 196
 197 * stdsux RS,RA,RB,SH
 198
 199 Pseudo-code:
 200
 201     EA <- (RA) + (RB) << (SH+1)
 202     MEM(EA, 8) <- (RS)
 203     RA <- EA
 204
 205 Description:
 206
 207     Let the effective address (EA) be the sum (RA)+ (RB).
 208     (RS) is stored into the doubleword in storage
 209     addressed by EA.
 210
 211     EA is placed into register RA.
 212
 213     If RA=0, the instruction form is invalid.
 214
 215 Special Registers Altered:
 216
 217     None
 218
 219
 220 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 221
 222 # Store Halfword Byte-Reverse Shifted Indexed
 223
 224 X-Form
 225
 226 * sthbrsx RS,RA,RB,SH
 227
 228 Pseudo-code:
 229
 230     b <- (RA|0)
 231     EA <- b + (RB) << (SH+1)
 232     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 233
 234 Description:
 235
 236     Let the effective address (EA) be the sum
 237     (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
 238     halfword in storage addressed by EA. (RS) 48:55 are
 239     stored into bits 8:15 of the halfword in storage
 240     addressed by EA.
 241
 242 Special Registers Altered:
 243
 244     None
 245
 246 # Store Word Byte-Reverse Shifted Indexed
 247
 248 X-Form
 249
 250 * stwbrsx RS,RA,RB,SH
 251
 252 Pseudo-code:
 253
 254     b <- (RA|0)
 255     EA <- b + (RB) << (SH+1)
 256     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 257                    ||(RS)[32:39])
 258
 259 Description:
 260
 261     Let the effective address (EA) be the sum
 262     (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
 263     word in storage addressed by EA. (RS) [48:55] are stored
 264     into bits 8:15 of the word in storage addressed by EA.
 265     (RS)[40:47] are stored into bits 16:23 of the word in stor-
 266     age addressed by EA. (RS) [32:39] are stored into bits
 267     24:31 of the word in storage addressed by EA.
 268
 269 Special Registers Altered:
 270
 271     None
 272
 273 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 274
 275 # Store Doubleword Byte-Reverse Shifted Indexed
 276
 277 X-Form
 278
 279 * stdbrsx RS,RA,RB,SH
 280
 281 Pseudo-code:
 282
 283     b <- (RA|0)
 284     EA <- b + (RB) << (SH+1)
 285     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 286                     || (RS)[40:47] || (RS)[32:39]
 287                     || (RS)[24:31] || (RS)[16:23]
 288                     || (RS)[8:15]  || (RS)[0:7])
 289
 290 Description:
 291
 292     Let the effective address (EA) be the sum
 293     (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
 294     doubleword in storage addressed by EA. (RS) [48:55] are
 295     stored into bits 8:15 of the doubleword in storage
 296     addressed by EA. (RS) [40:47] are stored into bits 16:23 of
 297     the doubleword in storage addressed by EA. (RS) [32:39]
 298     are stored into bits 23:31 of the doubleword in storage
 299     addressed by EA. (RS) [24:31] are stored into bits 32:39 of
 300     the doubleword in storage addressed by EA. (RS) [16:23]
 301     are stored into bits 40:47 of the doubleword in storage
 302     addressed by EA. (RS)[8:15] are stored into bits 48:55 of
 303     the doubleword in storage addressed by EA. (RS) [0:7]
 304     are stored into bits 56:63 of the doubleword in storage
 305     addressed by EA.
 306
 307 Special Registers Altered:
 308
 309     None
 310
 311 <!-- Checked March 2021 -->