openpower/isa/fixedstoreshift.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4
   5 <!-- Note that these pages also define equivalent load instructions, -->
   6 <!-- these are described in fixedload.mdwn -->
   7
   8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
   9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
  10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
  11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
  12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
  13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
  14
  15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
  16
  17 # Store Byte Shifted Indexed
  18
  19 X-Form
  20
  21 * stbx RS,RA,RB,SH
  22
  23 Pseudo-code:
  24
  25     b <- (RA|0)
  26     EA <- b + (RB) << (SH+1)
  27     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  28
  29 Description:
  30
  31     Let the effective address (EA) be the sum
  32     (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
  33     age addressed by EA.
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Store Byte Shifted with Update Indexed
  40
  41 X-Form
  42
  43 * stbsux RS,RA,RB,SH
  44
  45 Pseudo-code:
  46
  47     EA <- (RA) + (RB) << (SH+1)
  48     MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
  49     RA <- EA
  50
  51 Description:
  52
  53     Let the effective address (EA) be the sum (RA)+ (RB).
  54     RS[56:63] are stored into the byte in storage addressed
  55     by EA.
  56
  57     EA is placed into register RA.
  58
  59     If RA=0, the instruction form is invalid.
  60
  61 Special Registers Altered:
  62
  63     None
  64
  65 # Store Halfword Indexed
  66
  67 X-Form
  68
  69 * sthx RS,RA,RB
  70
  71 Pseudo-code:
  72
  73     b <- (RA|0)
  74     EA <- b + (RB)
  75     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
  76
  77 Description:
  78
  79     Let the effective address (EA) be the sum
  80     (RA|0)+ (RB). RS[48:63] are stored into the halfword in
  81     storage addressed by EA.
  82
  83 Special Registers Altered:
  84
  85     None
  86
  87 # Store Halfword with Update Indexed
  88
  89 X-Form
  90
  91 * sthux RS,RA,RB
  92
  93 Pseudo-code:
  94
  95     EA <- (RA) + (RB)
  96     MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
  97     RA <- EA
  98
  99 Description:
 100
 101     Let the effective address (EA) be the sum (RA)+ (RB).
 102     RS[48:63] are stored into the halfword in storage
 103     addressed by EA.
 104
 105     EA is placed into register RA.
 106
 107     If RA=0, the instruction form is invalid.
 108
 109 Special Registers Altered:
 110
 111     None
 112
 113 # Store Word Indexed
 114
 115 X-Form
 116
 117 * stwx RS,RA,RB
 118
 119 Pseudo-code:
 120
 121     b <- (RA|0)
 122     EA <- b + (RB)
 123     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 124
 125 Description:
 126
 127     Let the effective address (EA) be the sum
 128     (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
 129     age addressed by EA.
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Store Word with Update Indexed
 136
 137 X-Form
 138
 139 * stwux RS,RA,RB
 140
 141 Pseudo-code:
 142
 143     EA <- (RA) + (RB)
 144     MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
 145     RA <- EA
 146
 147 Description:
 148
 149     Let the effective address (EA) be the sum (RA)+ (RB).
 150     RS[32:63] are stored into the word in storage addressed
 151     by EA.
 152
 153     EA is placed into register RA.
 154
 155     If RA=0, the instruction form is invalid.
 156
 157 Special Registers Altered:
 158
 159     None
 160
 161
 162
 163 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
 164
 165 # Store Doubleword Indexed
 166
 167 X-Form
 168
 169 * stdx RS,RA,RB
 170
 171 Pseudo-code:
 172
 173     b <- (RA|0)
 174     EA <- b + (RB)
 175     MEM(EA, 8) <- (RS)
 176
 177 Description:
 178
 179     Let the effective address (EA) be the sum
 180     (RA|0)+ (RB). (RS) is stored into the doubleword in
 181     storage addressed by EA.
 182
 183 Special Registers Altered:
 184
 185     None
 186
 187 # Store Doubleword with Update Indexed
 188
 189 X-Form
 190
 191 * stdux RS,RA,RB
 192
 193 Pseudo-code:
 194
 195     EA <- (RA) + (RB)
 196     MEM(EA, 8) <- (RS)
 197     RA <- EA
 198
 199 Description:
 200
 201     Let the effective address (EA) be the sum (RA)+ (RB).
 202     (RS) is stored into the doubleword in storage
 203     addressed by EA.
 204
 205     EA is placed into register RA.
 206
 207     If RA=0, the instruction form is invalid.
 208
 209 Special Registers Altered:
 210
 211     None
 212
 213
 214 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 215
 216 # Store Halfword Byte-Reverse Indexed
 217
 218 X-Form
 219
 220 * sthbrx RS,RA,RB
 221
 222 Pseudo-code:
 223
 224     b <- (RA|0)
 225     EA <- b + (RB)
 226     MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
 227
 228 Description:
 229
 230     Let the effective address (EA) be the sum
 231     (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
 232     halfword in storage addressed by EA. (RS) 48:55 are
 233     stored into bits 8:15 of the halfword in storage
 234     addressed by EA.
 235
 236 Special Registers Altered:
 237
 238     None
 239
 240 # Store Word Byte-Reverse Indexed
 241
 242 X-Form
 243
 244 * stwbrx RS,RA,RB
 245
 246 Pseudo-code:
 247
 248     b <- (RA|0)
 249     EA <- b + (RB)
 250     MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
 251                    ||(RS)[32:39])
 252
 253 Description:
 254
 255     Let the effective address (EA) be the sum
 256     (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
 257     word in storage addressed by EA. (RS) [48:55] are stored
 258     into bits 8:15 of the word in storage addressed by EA.
 259     (RS)[40:47] are stored into bits 16:23 of the word in stor-
 260     age addressed by EA. (RS) [32:39] are stored into bits
 261     24:31 of the word in storage addressed by EA.
 262
 263 Special Registers Altered:
 264
 265     None
 266
 267 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 268
 269 # Store Doubleword Byte-Reverse Indexed
 270
 271 X-Form
 272
 273 * stdbrx RS,RA,RB
 274
 275 Pseudo-code:
 276
 277     b <- (RA|0)
 278     EA <- b + (RB)
 279     MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
 280                     || (RS)[40:47] || (RS)[32:39]
 281                     || (RS)[24:31] || (RS)[16:23]
 282                     || (RS)[8:15]  || (RS)[0:7])
 283
 284 Description:
 285
 286     Let the effective address (EA) be the sum
 287     (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
 288     doubleword in storage addressed by EA. (RS) [48:55] are
 289     stored into bits 8:15 of the doubleword in storage
 290     addressed by EA. (RS) [40:47] are stored into bits 16:23 of
 291     the doubleword in storage addressed by EA. (RS) [32:39]
 292     are stored into bits 23:31 of the doubleword in storage
 293     addressed by EA. (RS) [24:31] are stored into bits 32:39 of
 294     the doubleword in storage addressed by EA. (RS) [16:23]
 295     are stored into bits 40:47 of the doubleword in storage
 296     addressed by EA. (RS)[8:15] are stored into bits 48:55 of
 297     the doubleword in storage addressed by EA. (RS) [0:7]
 298     are stored into bits 56:63 of the doubleword in storage
 299     addressed by EA.
 300
 301 Special Registers Altered:
 302
 303     None
 304
 305 <!-- Checked March 2021 -->