1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that store from a register to RAM -->
5 <!-- Note that these pages also define equivalent load instructions, -->
6 <!-- these are described in fixedload.mdwn -->
8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
27 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
31 Let the effective address (EA) be the sum
32 (RA|0)+ (RB). RS [56:63] are stored into the byte in stor-
35 Special Registers Altered:
39 # Store Byte with Update Indexed
48 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
53 Let the effective address (EA) be the sum (RA)+ (RB).
54 RS[56:63] are stored into the byte in storage addressed
57 EA is placed into register RA.
59 If RA=0, the instruction form is invalid.
61 Special Registers Altered:
65 # Store Halfword Indexed
75 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
79 Let the effective address (EA) be the sum
80 (RA|0)+ (RB). RS[48:63] are stored into the halfword in
81 storage addressed by EA.
83 Special Registers Altered:
87 # Store Halfword with Update Indexed
96 MEM(EA, 2) <- (RS)[XLEN-16:XLEN-1]
101 Let the effective address (EA) be the sum (RA)+ (RB).
102 RS[48:63] are stored into the halfword in storage
105 EA is placed into register RA.
107 If RA=0, the instruction form is invalid.
109 Special Registers Altered:
123 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
127 Let the effective address (EA) be the sum
128 (RA|0)+ (RB). RS[32:63] are stored into the word in stor-
131 Special Registers Altered:
135 # Store Word with Update Indexed
144 MEM(EA, 4) <- (RS)[XLEN-32:XLEN-1]
149 Let the effective address (EA) be the sum (RA)+ (RB).
150 RS[32:63] are stored into the word in storage addressed
153 EA is placed into register RA.
155 If RA=0, the instruction form is invalid.
157 Special Registers Altered:
163 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
165 # Store Doubleword Indexed
179 Let the effective address (EA) be the sum
180 (RA|0)+ (RB). (RS) is stored into the doubleword in
181 storage addressed by EA.
183 Special Registers Altered:
187 # Store Doubleword with Update Indexed
201 Let the effective address (EA) be the sum (RA)+ (RB).
202 (RS) is stored into the doubleword in storage
205 EA is placed into register RA.
207 If RA=0, the instruction form is invalid.
209 Special Registers Altered:
214 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
216 # Store Halfword Byte-Reverse Indexed
226 MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
230 Let the effective address (EA) be the sum
231 (RA|0)+ (RB). (RS)56:63 are stored into bits 0:7 of the
232 halfword in storage addressed by EA. (RS) 48:55 are
233 stored into bits 8:15 of the halfword in storage
236 Special Registers Altered:
240 # Store Word Byte-Reverse Indexed
250 MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
255 Let the effective address (EA) be the sum
256 (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
257 word in storage addressed by EA. (RS) [48:55] are stored
258 into bits 8:15 of the word in storage addressed by EA.
259 (RS)[40:47] are stored into bits 16:23 of the word in stor-
260 age addressed by EA. (RS) [32:39] are stored into bits
261 24:31 of the word in storage addressed by EA.
263 Special Registers Altered:
267 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
269 # Store Doubleword Byte-Reverse Indexed
279 MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
280 || (RS)[40:47] || (RS)[32:39]
281 || (RS)[24:31] || (RS)[16:23]
282 || (RS)[8:15] || (RS)[0:7])
286 Let the effective address (EA) be the sum
287 (RA|0)+ (RB). (RS)[56:63] are stored into bits 0:7 of the
288 doubleword in storage addressed by EA. (RS) [48:55] are
289 stored into bits 8:15 of the doubleword in storage
290 addressed by EA. (RS) [40:47] are stored into bits 16:23 of
291 the doubleword in storage addressed by EA. (RS) [32:39]
292 are stored into bits 23:31 of the doubleword in storage
293 addressed by EA. (RS) [24:31] are stored into bits 32:39 of
294 the doubleword in storage addressed by EA. (RS) [16:23]
295 are stored into bits 40:47 of the doubleword in storage
296 addressed by EA. (RS)[8:15] are stored into bits 48:55 of
297 the doubleword in storage addressed by EA. (RS) [0:7]
298 are stored into bits 56:63 of the doubleword in storage
301 Special Registers Altered:
305 <!-- Checked March 2021 -->