1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
3 <!-- Section 4.6.7 Floating-point Rounding and Conversion instructions. P 159 - 166 -->
5 # Floating Convert with round Signed Doubleword to Single-Precision format
9 * fcfids FRT,FRB (Rc=0)
10 * fcfids. FRT,FRB (Rc=1)
14 FRT <- INT2FP(FRB, 'sint2single')
16 Special Registers Altered:
22 # [DRAFT] Floating Convert From Integer In GPR
26 * fcvtfg FRT,RB,IT (Rc=0)
27 * fcvtfg. FRT,RB,IT (Rc=1)
31 if IT[0] = 0 then # 32-bit int -> 64-bit float
32 # rounding never necessary, so don't touch FPSCR
34 if IT = 0 then # Signed 32-bit
35 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
36 else # IT = 1 -- Unsigned 32-bit
37 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
38 FRT <- bfp64_CONVERT_FROM_BFP(src)
40 # rounding may be necessary. based off xscvuxdsp
43 case(0): # Signed 32-bit
44 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
45 case(1): # Unsigned 32-bit
46 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
47 case(2): # Signed 64-bit
48 src <- bfp_CONVERT_FROM_SI64((RB))
49 default: # Unsigned 64-bit
50 src <- bfp_CONVERT_FROM_UI64((RB))
51 rnd <- bfp_ROUND_TO_BFP64(FPSCR.RN, src)
52 result <- bfp64_CONVERT_FROM_BFP(rnd)
53 cls <- fprf_CLASS_BFP64(result)
54 if xx_flag = 1 then SetFX(FPSCR.XX)
60 Special Registers Altered:
63 FPRF FR FI FX XX (if IT[0]=1)
65 # [DRAFT] Floating Convert From Integer In GPR Single
69 * fcvtfgs FRT,RB,IT (Rc=0)
70 * fcvtfgs. FRT,RB,IT (Rc=1)
74 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX, -->
75 <!-- don't remove them -->
76 # rounding may be necessary. based off xscvuxdsp
79 case(0): # Signed 32-bit
80 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
81 case(1): # Unsigned 32-bit
82 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
83 case(2): # Signed 64-bit
84 src <- bfp_CONVERT_FROM_SI64((RB))
85 default: # Unsigned 64-bit
86 src <- bfp_CONVERT_FROM_UI64((RB))
87 rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
88 result32 <- bfp32_CONVERT_FROM_BFP(rnd)
89 cls <- fprf_CLASS_BFP32(result32)
90 result <- DOUBLE(result32)
91 if xx_flag = 1 then SetFX(FPSCR.XX)
97 Special Registers Altered:
102 # [DRAFT] Floating Convert To Integer In GPR
106 * fcvttg RT,FRB,CVM,IT (OE=0 Rc=0)
107 * fcvttg. RT,FRB,CVM,IT (OE=0 Rc=1)
108 * fcvttgo RT,FRB,CVM,IT (OE=1 Rc=0)
109 * fcvttgo. RT,FRB,CVM,IT (OE=1 Rc=1)
113 # based on xscvdpuxws
115 src <- bfp_CONVERT_FROM_BFP64((FRB))
117 case(0): # Signed 32-bit
118 range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
119 range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
120 js_mask <- 0x0000_0000_FFFF_FFFF
121 case(1): # Unsigned 32-bit
122 range_min <- bfp_CONVERT_FROM_UI32(0)
123 range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
124 js_mask <- 0x0000_0000_FFFF_FFFF
125 case(2): # Signed 64-bit
126 range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
127 range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
128 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
129 default: # Unsigned 64-bit
130 range_min <- bfp_CONVERT_FROM_UI64(0)
131 range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
132 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
133 if (CVM[2] = 1) | (FPSCR.RN = 0b01) then
134 rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
135 else if FPSCR.RN = 0b00 then
136 rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
137 else if FPSCR.RN = 0b10 then
138 rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
139 else if FPSCR.RN = 0b11 then
140 rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
142 case(0, 1): # OpenPower semantics
144 result <- si64_CONVERT_FROM_BFP(range_min)
145 else if bfp_COMPARE_GT(rnd, range_max) then
146 result <- ui64_CONVERT_FROM_BFP(range_max)
147 else if bfp_COMPARE_LT(rnd, range_min) then
148 result <- si64_CONVERT_FROM_BFP(range_min)
149 else if IT[1] = 1 then # Unsigned 32/64-bit
150 result <- ui64_CONVERT_FROM_BFP(rnd)
151 else # Signed 32/64-bit
152 result <- si64_CONVERT_FROM_BFP(rnd)
153 case(2, 3): # Java/Saturating semantics
156 else if bfp_COMPARE_GT(rnd, range_max) then
157 result <- ui64_CONVERT_FROM_BFP(range_max)
158 else if bfp_COMPARE_LT(rnd, range_min) then
159 result <- si64_CONVERT_FROM_BFP(range_min)
160 else if IT[1] = 1 then # Unsigned 32/64-bit
161 result <- ui64_CONVERT_FROM_BFP(rnd)
162 else # Signed 32/64-bit
163 result <- si64_CONVERT_FROM_BFP(rnd)
164 default: # JavaScript semantics
165 # CVM = 6, 7 are illegal instructions
166 # using a 128-bit intermediate works here because the largest type
167 # this instruction can convert from has 53 significand bits, and
168 # the largest type this instruction can convert to has 64 bits,
169 # and the sum of those is strictly less than the 128 bits of the
170 # intermediate result.
171 limit <- bfp_CONVERT_FROM_UI128([1] * 128)
172 if IsInf(rnd) | IsNaN(rnd) then
174 else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
177 result128 <- si128_CONVERT_FROM_BFP(rnd)
178 result <- result128[64:127] & js_mask
180 case(0): # Signed 32-bit
181 result <- EXTS64(result[32:63])
182 result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
183 case(1): # Unsigned 32-bit
184 result <- EXTZ64(result[32:63])
185 result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
186 case(2): # Signed 64-bit
187 result_bfp <- bfp_CONVERT_FROM_SI64(result)
188 default: # Unsigned 64-bit
189 result_bfp <- bfp_CONVERT_FROM_UI64(result)
190 overflow <- 0 # signals SO only when OE = 1
191 if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then
192 overflow <- 1 # signals SO only when OE = 1
195 else if ¬bfp_COMPARE_EQ(src, result_bfp) then
197 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
198 if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
199 if xx_flag = 1 then SetFX(FPSCR.XX)
200 vx_flag <- vxsnan_flag | vxcvi_flag
201 vex_flag <- FPSCR.VE & vx_flag
204 FPSCR.FPRF <- undefined(0b00000)
211 Special Registers Altered:
215 FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
217 # [DRAFT] Floating Convert To Integer In GPR Single
221 * fcvttgs RT,FRB,CVM,IT (OE=0 Rc=0)
222 * fcvttgs. RT,FRB,CVM,IT (OE=0 Rc=1)
223 * fcvttgso RT,FRB,CVM,IT (OE=1 Rc=0)
224 * fcvttgso. RT,FRB,CVM,IT (OE=1 Rc=1)
228 # based on xscvdpuxws
230 src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB)))
232 case(0): # Signed 32-bit
233 range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
234 range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
235 js_mask <- 0x0000_0000_FFFF_FFFF
236 case(1): # Unsigned 32-bit
237 range_min <- bfp_CONVERT_FROM_UI32(0)
238 range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
239 js_mask <- 0x0000_0000_FFFF_FFFF
240 case(2): # Signed 64-bit
241 range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
242 range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
243 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
244 default: # Unsigned 64-bit
245 range_min <- bfp_CONVERT_FROM_UI64(0)
246 range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
247 js_mask <- 0xFFFF_FFFF_FFFF_FFFF
248 if (CVM[2] = 1) | (FPSCR.RN = 0b01) then
249 rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
250 else if FPSCR.RN = 0b00 then
251 rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
252 else if FPSCR.RN = 0b10 then
253 rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
254 else if FPSCR.RN = 0b11 then
255 rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
257 case(0, 1): # OpenPower semantics
259 result <- si64_CONVERT_FROM_BFP(range_min)
260 else if bfp_COMPARE_GT(rnd, range_max) then
261 result <- ui64_CONVERT_FROM_BFP(range_max)
262 else if bfp_COMPARE_LT(rnd, range_min) then
263 result <- si64_CONVERT_FROM_BFP(range_min)
264 else if IT[1] = 1 then # Unsigned 32/64-bit
265 result <- ui64_CONVERT_FROM_BFP(rnd)
266 else # Signed 32/64-bit
267 result <- si64_CONVERT_FROM_BFP(rnd)
268 case(2, 3): # Java/Saturating semantics
271 else if bfp_COMPARE_GT(rnd, range_max) then
272 result <- ui64_CONVERT_FROM_BFP(range_max)
273 else if bfp_COMPARE_LT(rnd, range_min) then
274 result <- si64_CONVERT_FROM_BFP(range_min)
275 else if IT[1] = 1 then # Unsigned 32/64-bit
276 result <- ui64_CONVERT_FROM_BFP(rnd)
277 else # Signed 32/64-bit
278 result <- si64_CONVERT_FROM_BFP(rnd)
279 default: # JavaScript semantics
280 # CVM = 6, 7 are illegal instructions
281 # using a 128-bit intermediate works here because the largest type
282 # this instruction can convert from has 53 significand bits, and
283 # the largest type this instruction can convert to has 64 bits,
284 # and the sum of those is strictly less than the 128 bits of the
285 # intermediate result.
286 limit <- bfp_CONVERT_FROM_UI128([1] * 128)
287 if IsInf(rnd) | IsNaN(rnd) then
289 else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
292 result128 <- si128_CONVERT_FROM_BFP(rnd)
293 result <- result128[64:127] & js_mask
295 case(0): # Signed 32-bit
296 result <- EXTS64(result[32:63])
297 result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
298 case(1): # Unsigned 32-bit
299 result <- EXTZ64(result[32:63])
300 result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
301 case(2): # Signed 64-bit
302 result_bfp <- bfp_CONVERT_FROM_SI64(result)
303 default: # Unsigned 64-bit
304 result_bfp <- bfp_CONVERT_FROM_UI64(result)
305 overflow <- 0 # signals SO only when OE = 1
306 if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then
307 overflow <- 1 # signals SO only when OE = 1
310 else if ¬bfp_COMPARE_EQ(src, result_bfp) then
312 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
313 if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
314 if xx_flag = 1 then SetFX(FPSCR.XX)
315 vx_flag <- vxsnan_flag | vxcvi_flag
316 vex_flag <- FPSCR.VE & vx_flag
319 FPSCR.FPRF <- undefined(0b00000)
326 Special Registers Altered:
330 FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV