openpower/isa/fpcvt.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.7 Floating-point Rounding and Conversion instructions. P 159 - 166 -->
   4
   5 # Floating Convert with round Signed Doubleword to Single-Precision format
   6
   7 X-Form
   8
   9 * fcfids  FRT,FRB (Rc=0)
  10 * fcfids. FRT,FRB (Rc=1)
  11
  12 Pseudo-code:
  13
  14     FRT <- INT2FP(FRB, 'sint2single')
  15
  16 Special Registers Altered:
  17
  18     FPRF FR FI
  19     FX XX
  20     CR1        (if Rc=1)
  21
  22 # [DRAFT] Floating Convert From Integer In GPR
  23
  24 X-Form
  25
  26 * ctfpr FRT,RB,IT (Rc=0)
  27 * ctfpr. FRT,RB,IT (Rc=1)
  28
  29 Pseudo-code:
  30
  31     if IT[0] = 0 then  # 32-bit int -> 64-bit float
  32         # rounding never necessary, so don't touch FPSCR
  33         # based off xvcvsxwdp
  34         if IT = 0 then  # Signed 32-bit
  35             src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
  36         else  # IT = 1 -- Unsigned 32-bit
  37             src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
  38         FRT <- bfp64_CONVERT_FROM_BFP(src)
  39     else
  40         # rounding may be necessary. based off xscvuxdsp
  41         reset_xflags()
  42         switch(IT)
  43             case(0):  # Signed 32-bit
  44                 src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
  45             case(1):  # Unsigned 32-bit
  46                 src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
  47             case(2):  # Signed 64-bit
  48                 src <- bfp_CONVERT_FROM_SI64((RB))
  49             default:  # Unsigned 64-bit
  50                 src <- bfp_CONVERT_FROM_UI64((RB))
  51         rnd <- bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, src)
  52         result <- bfp64_CONVERT_FROM_BFP(rnd)
  53         cls <- fprf_CLASS_BFP64(result)
  54         if xx_flag = 1 then SetFX(FPSCR.XX)
  55         FRT <- result
  56         FPSCR.FPRF <- cls
  57         FPSCR.FR <- inc_flag
  58         FPSCR.FI <- xx_flag
  59
  60 Special Registers Altered:
  61
  62     CR1          (if Rc=1)
  63     FPRF FR FI FX XX  (if IT[0]=1)
  64
  65 # [DRAFT] Floating Convert From Integer In GPR Single
  66
  67 X-Form
  68
  69 * ctfprs FRT,RB,IT (Rc=0)
  70 * ctfprs. FRT,RB,IT (Rc=1)
  71
  72 Pseudo-code:
  73
  74 <!-- note the PowerISA spec. explicitly has empty lines before/after SetFX, -->
  75 <!-- don't remove them -->
  76     # rounding may be necessary. based off xscvuxdsp
  77     reset_xflags()
  78     switch(IT)
  79         case(0):  # Signed 32-bit
  80             src <- bfp_CONVERT_FROM_SI32((RB)[32:63])
  81         case(1):  # Unsigned 32-bit
  82             src <- bfp_CONVERT_FROM_UI32((RB)[32:63])
  83         case(2):  # Signed 64-bit
  84             src <- bfp_CONVERT_FROM_SI64((RB))
  85         default:  # Unsigned 64-bit
  86             src <- bfp_CONVERT_FROM_UI64((RB))
  87     rnd <- bfp_ROUND_TO_BFP32(FPSCR.RN, src)
  88     result32 <- bfp32_CONVERT_FROM_BFP(rnd)
  89     cls <- fprf_CLASS_BFP32(result32)
  90     result <- DOUBLE(result32)
  91     if xx_flag = 1 then SetFX(FPSCR.XX)
  92     FRT <- result
  93     FPSCR.FPRF <- cls
  94     FPSCR.FR <- inc_flag
  95     FPSCR.FI <- xx_flag
  96
  97 Special Registers Altered:
  98
  99     CR1          (if Rc=1)
 100     FPRF FR FI FX XX
 101
 102 # [DRAFT] Floating Convert To Integer In GPR
 103
 104 XO-Form
 105
 106 * cffpr RT,FRB,CVM,IT (OE=0 Rc=0)
 107 * cffpr. RT,FRB,CVM,IT (OE=0 Rc=1)
 108 * cffpro RT,FRB,CVM,IT (OE=1 Rc=0)
 109 * cffpro. RT,FRB,CVM,IT (OE=1 Rc=1)
 110
 111 Pseudo-code:
 112
 113 <!-- EXTRA_UNINIT_REGS: RT -->
 114     # based on xscvdpuxws
 115     reset_xflags()
 116     src <- bfp_CONVERT_FROM_BFP64((FRB))
 117     switch(IT)
 118         case(0):  # Signed 32-bit
 119             range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
 120             range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
 121             js_mask <- 0x0000_0000_FFFF_FFFF
 122         case(1):  # Unsigned 32-bit
 123             range_min <- bfp_CONVERT_FROM_UI32(0)
 124             range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
 125             js_mask <- 0x0000_0000_FFFF_FFFF
 126         case(2):  # Signed 64-bit
 127             range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
 128             range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
 129             js_mask <- 0xFFFF_FFFF_FFFF_FFFF
 130         default:  # Unsigned 64-bit
 131             range_min <- bfp_CONVERT_FROM_UI64(0)
 132             range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
 133             js_mask <- 0xFFFF_FFFF_FFFF_FFFF
 134     if (CVM[2] = 1) | (FPSCR.RN = 0b01) then
 135         rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
 136     else if FPSCR.RN = 0b00 then
 137         rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
 138     else if FPSCR.RN = 0b10 then
 139         rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
 140     else if FPSCR.RN = 0b11 then
 141         rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
 142     switch(CVM)
 143         case(0, 1):  # OpenPower semantics
 144             if IsNaN(rnd) then
 145                 result <- si64_CONVERT_FROM_BFP(range_min)
 146             else if bfp_COMPARE_GT(rnd, range_max) then
 147                 result <- ui64_CONVERT_FROM_BFP(range_max)
 148             else if bfp_COMPARE_LT(rnd, range_min) then
 149                 result <- si64_CONVERT_FROM_BFP(range_min)
 150             else if IT[1] = 1 then  # Unsigned 32/64-bit
 151                 result <- ui64_CONVERT_FROM_BFP(rnd)
 152             else  # Signed 32/64-bit
 153                 result <- si64_CONVERT_FROM_BFP(rnd)
 154         case(2, 3):  # Java/Saturating semantics
 155             if IsNaN(rnd) then
 156                 result <- [0] * 64
 157             else if bfp_COMPARE_GT(rnd, range_max) then
 158                 result <- ui64_CONVERT_FROM_BFP(range_max)
 159             else if bfp_COMPARE_LT(rnd, range_min) then
 160                 result <- si64_CONVERT_FROM_BFP(range_min)
 161             else if IT[1] = 1 then  # Unsigned 32/64-bit
 162                 result <- ui64_CONVERT_FROM_BFP(rnd)
 163             else  # Signed 32/64-bit
 164                 result <- si64_CONVERT_FROM_BFP(rnd)
 165         default:  # JavaScript semantics
 166             # CVM = 6, 7 are illegal instructions
 167             # using a 128-bit intermediate works here because the largest type
 168             # this instruction can convert from has 53 significand bits, and
 169             # the largest type this instruction can convert to has 64 bits,
 170             # and the sum of those is strictly less than the 128 bits of the
 171             # intermediate result.
 172             limit <- bfp_CONVERT_FROM_UI128([1] * 128)
 173             if IsInf(rnd) | IsNaN(rnd) then
 174                 result <- [0] * 64
 175             else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
 176                 result <- [0] * 64
 177             else
 178                 result128 <- si128_CONVERT_FROM_BFP(rnd)
 179                 result <- result128[64:127] & js_mask
 180     switch(IT)
 181         case(0):  # Signed 32-bit
 182             result <- EXTS64(result[32:63])
 183             result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
 184         case(1):  # Unsigned 32-bit
 185             result <- EXTZ64(result[32:63])
 186             result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
 187         case(2):  # Signed 64-bit
 188             result_bfp <- bfp_CONVERT_FROM_SI64(result)
 189         default:  # Unsigned 64-bit
 190             result_bfp <- bfp_CONVERT_FROM_UI64(result)
 191     overflow <- 0  # signals SO only when OE = 1
 192     if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then
 193         overflow <- 1  # signals SO only when OE = 1
 194         vxcvi_flag <- 1
 195         xx_flag <- 0
 196         inc_flag <- 0
 197     else
 198         xx_flag <- ¬bfp_COMPARE_EQ(src, result_bfp)
 199         inc_flag <- bfp_COMPARE_GT(bfp_ABSOLUTE(result_bfp), bfp_ABSOLUTE(src))
 200     if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
 201     if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
 202     if xx_flag = 1 then SetFX(FPSCR.XX)
 203     vx_flag <- vxsnan_flag | vxcvi_flag
 204     vex_flag <- FPSCR.VE & vx_flag
 205     if vex_flag = 0 then
 206         RT <- result
 207         FPSCR.FPRF <- undefined(0b00000)
 208         FPSCR.FR <- inc_flag
 209         FPSCR.FI <- xx_flag
 210     else
 211         FPSCR.FR <- 0
 212         FPSCR.FI <- 0
 213
 214 Special Registers Altered:
 215
 216     CR0                     (if Rc=1)
 217     SO OV OV32              (if OE=1)
 218     FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV