openpower/isa/fpload.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
   4
   5 # Load Floating-Point Single
   6
   7 D-Form
   8
   9 * lfs FRT,D(RA)
  10
  11 Pseudo-code:
  12
  13     EA <- (RA|0) + EXTS(D)
  14     FRT <- DOUBLE(MEM(EA, 4))
  15
  16 Description:
  17
  18     Let the effective address (EA) be the sum (RA|0)+D.
  19
  20     The word in storage addressed by EA is interpreted as
  21     a floating-point single-precision operand. This word is
  22     converted to floating-point double format (see
  23     page 138) and placed into register FRT.
  24
  25 Special Registers Altered:
  26
  27     None
  28
  29 # Load Floating-Point Single Indexed
  30
  31 X-Form
  32
  33 * lfsx FRT,RA,RB
  34
  35 Pseudo-code:
  36
  37     EA <- (RA|0) + (RB)
  38     FRT <- DOUBLE(MEM(EA, 4))
  39
  40 Description:
  41
  42     Let the effective address (EA) be the sum (RA|0)+(RB).
  43
  44     The word in storage addressed by EA is interpreted as
  45     a floating-point single-precision operand. This word is
  46     converted to floating-point double format (see
  47     page 138) and placed into register FRT.
  48
  49 Special Registers Altered:
  50
  51     None
  52
  53 # Load Floating-Point Single with Update
  54
  55 D-Form
  56
  57 * lfsu FRT,D(RA)
  58
  59 Pseudo-code:
  60
  61     EA <- (RA) + EXTS(D)
  62     FRT <- DOUBLE(MEM(EA, 4))
  63     RA <- EA
  64
  65 Description:
  66
  67     Let the effective address (EA) be the sum (RA)+D.
  68
  69     The word in storage addressed by EA is interpreted as
  70     a floating-point single-precision operand. This word is
  71     converted to floating-point double format (see
  72     page 138) and placed into register FRT.
  73
  74     EA is placed into register RA.
  75
  76     If RA=0, the instruction form is invalid.
  77
  78 Special Registers Altered:
  79
  80     None
  81
  82 # Load Floating-Point Single with Update Indexed
  83
  84 X-Form
  85
  86 * lfsux FRT,RA,RB
  87
  88 Pseudo-code:
  89
  90     EA <- (RA) + (RB)
  91     FRT <- DOUBLE(MEM(EA, 4))
  92     RA <- EA
  93
  94 Description:
  95
  96     Let the effective address (EA) be the sum (RA)+(RB).
  97
  98     The word in storage addressed by EA is interpreted as
  99     a floating-point single-precision operand. This word is
 100     converted to floating-point double format (see
 101     page 138) and placed into register FRT.
 102
 103     EA is placed into register RA.
 104
 105     If RA=0, the instruction form is invalid.
 106
 107 Special Registers Altered:
 108
 109     None
 110
 111 # Load Floating-Point Double
 112
 113 D-Form
 114
 115 * lfd FRT,D(RA)
 116
 117 Pseudo-code:
 118
 119     EA <- (RA|0) + EXTS(D)
 120     FRT <- MEM(EA, 8)
 121
 122 Description:
 123
 124     Let the effective address (EA) be the sum (RA|0)+D.
 125
 126     The doubleword in storage addressed by EA is loaded
 127     into register FRT.
 128
 129 Special Registers Altered:
 130
 131     None
 132
 133 # Load Floating-Point Double Indexed
 134
 135 X-Form
 136
 137 * lfdx FRT,RA,RB
 138
 139 Pseudo-code:
 140
 141     EA <- (RA|0) + (RB)
 142     FRT <- MEM(EA, 8)
 143
 144 Description:
 145
 146     Let the effective address (EA) be the sum (RA|0)+(RB).
 147
 148     The doubleword in storage addressed by EA is loaded
 149     into register FRT.
 150
 151 Special Registers Altered:
 152
 153     None
 154
 155 # Load Floating-Point Double with Update
 156
 157 D-Form
 158
 159 * lfdu FRT,D(RA)
 160
 161 Pseudo-code:
 162
 163     EA <- (RA) + EXTS(D)
 164     FRT <- MEM(EA, 8)
 165     RA <- EA
 166
 167 Description:
 168
 169     Let the effective address (EA) be the sum (RA)+D.
 170
 171     The doubleword in storage addressed by EA is loaded
 172     into register FRT.
 173
 174     EA is placed into register RA.
 175
 176     If RA=0, the instruction form is invalid.
 177
 178 Special Registers Altered:
 179
 180     None
 181
 182 # Load Floating-Point Double with Update Indexed
 183
 184 X-Form
 185
 186 * lfdux FRT,RA,RB
 187
 188 Pseudo-code:
 189
 190     EA <- (RA) + (RB)
 191     FRT <- MEM(EA, 8)
 192     RA <- EA
 193
 194 Description:
 195
 196     Let the effective address (EA) be the sum (RA)+(RB).
 197
 198     The doubleword in storage addressed by EA is loaded
 199     into register FRT.
 200
 201     EA is placed into register RA.
 202
 203     If RA=0, the instruction form is invalid.
 204
 205 Special Registers Altered:
 206
 207     None
 208
 209 # Load Floating-Point as Integer Word Algebraic Indexed
 210
 211 X-Form
 212
 213 * lfiwax FRT,RA,RB
 214
 215 Pseudo-code:
 216
 217     EA <- (RA|0) + (RB)
 218     FRT <- EXTS(MEM(EA, 4))
 219
 220 Description:
 221
 222     Let the effective address (EA) be the sum (RA|0)+(RB).
 223
 224     The word in storage addressed by EA is loaded into
 225     FRT [32:63]. FRT [0:31] are filled with a copy of bit 0 of the
 226     loaded word.
 227
 228 Special Registers Altered:
 229
 230     None
 231
 232 # Load Floating-Point as Integer Word Zero Indexed
 233
 234 X-Form
 235
 236 * lfiwzx FRT,RA,RB
 237
 238 Pseudo-code:
 239
 240     EA <- (RA|0) + (RB)
 241     FRT <- [0]*32 || MEM(EA, 4)
 242
 243 Description:
 244
 245     Let the effective address (EA) be the sum (RA|0)+(RB).
 246
 247     The word in storage addressed by EA is loaded into
 248     FRT [32:63]. FRT [0:31] are set to 0.
 249
 250 Special Registers Altered:
 251
 252     None