openpower/isa/fpload.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
   4
   5 # Load Floating-Point Single
   6
   7 D-Form
   8
   9 * lfs FRT,D(RA)
  10
  11 Pseudo-code:
  12
  13     EA <- (RA|0) + EXTS(D)
  14     FRT <- DOUBLE(MEM(EA, 4))
  15
  16 Description:
  17
  18     Let the effective address (EA) be the sum (RA|0)+D.
  19     The word in storage addressed by EA is interpreted as
  20     a floating-point single-precision operand. This word is
  21     converted to floating-point double format (see
  22     page 138) and placed into register FRT.
  23
  24 Special Registers Altered:
  25
  26     None
  27
  28 # Load Floating-Point Single Indexed
  29
  30 X-Form
  31
  32 * lfsx FRT,RA,RB
  33
  34 Pseudo-code:
  35
  36     EA <- (RA|0) + (RB)
  37     FRT <- DOUBLE(MEM(EA, 4))
  38
  39 Description:
  40
  41     Let the effective address (EA) be the sum (RA|0)+(RB).
  42
  43     The word in storage addressed by EA is interpreted as
  44     a floating-point single-precision operand. This word is
  45     converted to floating-point double format (see
  46     page 138) and placed into register FRT.
  47
  48 Special Registers Altered:
  49
  50     None
  51
  52 # Load Floating-Point Single with Update
  53
  54 D-Form
  55
  56 * lfsu FRT,D(RA)
  57
  58 Pseudo-code:
  59
  60     EA <- (RA) + EXTS(D)
  61     FRT <- DOUBLE(MEM(EA, 4))
  62     RA <- EA
  63
  64 Description:
  65
  66     Let the effective address (EA) be the sum (RA)+D.
  67
  68     The word in storage addressed by EA is interpreted as
  69     a floating-point single-precision operand. This word is
  70     converted to floating-point double format (see
  71     page 138) and placed into register FRT.
  72
  73     EA is placed into register RA.
  74
  75     If RA=0, the instruction form is invalid.
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Load Floating-Point Single with Update Indexed
  82
  83 X-Form
  84
  85 * lfsux FRT,RA,RB
  86
  87 Pseudo-code:
  88
  89     EA <- (RA) + (RB)
  90     FRT <- DOUBLE(MEM(EA, 4))
  91     RA <- EA
  92
  93 Description:
  94
  95     Let the effective address (EA) be the sum (RA)+(RB).
  96
  97     The word in storage addressed by EA is interpreted as
  98     a floating-point single-precision operand. This word is
  99     converted to floating-point double format (see
 100     page 138) and placed into register FRT.
 101
 102     EA is placed into register RA.
 103
 104     If RA=0, the instruction form is invalid.
 105
 106 Special Registers Altered:
 107
 108     None
 109
 110 # Load Floating-Point Double
 111
 112 D-Form
 113
 114 * lfd FRT,D(RA)
 115
 116 Pseudo-code:
 117
 118     EA <- (RA|0) + EXTS(D)
 119     FRT <- MEM(EA, 8)
 120
 121 Description:
 122
 123     Let the effective address (EA) be the sum (RA|0)+D.
 124
 125     The doubleword in storage addressed by EA is loaded
 126     into register FRT.
 127
 128 Special Registers Altered:
 129
 130     None
 131
 132 # Load Floating-Point Double Indexed
 133
 134 X-Form
 135
 136 * lfdx FRT,RA,RB
 137
 138 Pseudo-code:
 139
 140     EA <- (RA|0) + (RB)
 141     FRT <- MEM(EA, 8)
 142
 143 Description:
 144
 145     Let the effective address (EA) be the sum (RA|0)+(RB).
 146
 147     The doubleword in storage addressed by EA is loaded
 148     into register FRT.
 149
 150 Special Registers Altered:
 151
 152     None
 153
 154 # Load Floating-Point Double with Update
 155
 156 D-Form
 157
 158 * lfdu FRT,D(RA)
 159
 160 Pseudo-code:
 161
 162     EA <- (RA) + EXTS(D)
 163     FRT <- MEM(EA, 8)
 164     RA <- EA
 165
 166 Special Registers Altered:
 167
 168     None
 169
 170 # Load Floating-Point Double with Update Indexed
 171
 172 X-Form
 173
 174 * lfdux FRT,RA,RB
 175
 176 Pseudo-code:
 177
 178     EA <- (RA) + (RB)
 179     FRT <- MEM(EA, 8)
 180     RA <- EA
 181
 182 Special Registers Altered:
 183
 184     None
 185
 186 # Load Floating-Point as Integer Word Algebraic Indexed
 187
 188 X-Form
 189
 190 * lfiwax FRT,RA,RB
 191
 192 Pseudo-code:
 193
 194     EA <- (RA|0) + (RB)
 195     FRT <- EXTS(MEM(EA, 4))
 196
 197 Special Registers Altered:
 198
 199     None
 200
 201 # Load Floating-Point as Integer Word Zero Indexed
 202
 203 X-Form
 204
 205 * lfiwzx FRT,RA,RB
 206
 207 Pseudo-code:
 208
 209     EA <- (RA|0) + (RB)
 210     FRT <- [0]*32 || MEM(EA, 4)
 211
 212 Special Registers Altered:
 213
 214     None