openpower/isa/fploadshift.mdwn

   1 <!-- DRAFT Floating-point Shifted storage access instructions. -->
   2
   3 # Load Floating-Point Single Indexed Shifted
   4
   5 X-Form
   6
   7 * lfssx FRT,RA,RB,SH
   8
   9 Pseudo-code:
  10
  11     EA <- (RA|0) + (RB)<<(SH+1)
  12     FRT <- DOUBLE(MEM(EA, 4))
  13
  14 Description:
  15
  16     Let the effective address (EA) be the sum of (RA|0) with
  17     the contents of register RB shifted by (SH+1).
  18
  19     The word in storage addressed by EA is interpreted as
  20     a floating-point single-precision operand. This word is
  21     converted to floating-point double format (see
  22     page 138) and placed into register FRT.
  23
  24 Special Registers Altered:
  25
  26     None
  27
  28 # Load Floating-Point Single with Update Indexed Shifted
  29
  30 X-Form
  31
  32 * lfsusx FRT,RA,RB,SH
  33
  34 Pseudo-code:
  35
  36     EA <- (RA) + (RB)<<(SH+1)
  37     FRT <- DOUBLE(MEM(EA, 4))
  38     RA <- EA
  39
  40 Description:
  41
  42     Let the effective address (EA) be the sum of the contents of
  43     register RB shifted by (SH+1), and the contents of register RA.
  44
  45     The word in storage addressed by EA is interpreted as
  46     a floating-point single-precision operand. This word is
  47     converted to floating-point double format (see
  48     page 138) and placed into register FRT.
  49
  50     EA is placed into register RA.
  51
  52     If RA=0, the instruction form is invalid.
  53
  54 Special Registers Altered:
  55
  56     None
  57
  58 # Load Floating-Point Double Indexed Shifted
  59
  60 X-Form
  61
  62 * lfdsx FRT,RA,RB,SH
  63
  64 Pseudo-code:
  65
  66     EA <- (RA|0) + (RB)<<(SH+1)
  67     FRT <- MEM(EA, 8)
  68
  69 Description:
  70
  71     Let the effective address (EA) be the sum of (RA|0) with
  72     the contents of register RB shifted by (SH+1).
  73
  74     The doubleword in storage addressed by EA is loaded
  75     into register FRT.
  76
  77 Special Registers Altered:
  78
  79     None
  80
  81 # Load Floating-Point Double with Update Indexed
  82
  83 X-Form
  84
  85 * lfdusx FRT,RA,RB,SH
  86
  87 Pseudo-code:
  88
  89     EA <- (RA) + (RB)<<(SH+1)
  90     FRT <- MEM(EA, 8)
  91     RA <- EA
  92
  93 Description:
  94
  95     Let the effective address (EA) be the sum of the contents of
  96     register RB shifted by (SH+1), and the contents of register RA.
  97
  98     The doubleword in storage addressed by EA is loaded
  99     into register FRT.
 100
 101     EA is placed into register RA.
 102
 103     If RA=0, the instruction form is invalid.
 104
 105 Special Registers Altered:
 106
 107     None
 108
 109 # Load Floating-Point as Integer Word Algebraic Indexed Shifted
 110
 111 X-Form
 112
 113 * lfiwasx FRT,RA,RB,SH
 114
 115 Pseudo-code:
 116
 117     EA <- (RA|0) + (RB)<<(SH+1)
 118     FRT <- EXTS(MEM(EA, 4))
 119
 120 Description:
 121
 122     Let the effective address (EA) be the sum of (RA|0) with
 123     the contents of register RB shifted by (SH+1).
 124
 125     The word in storage addressed by EA is loaded into
 126     FRT [32:63]. FRT [0:31] are filled with a copy of bit 0 of the
 127     loaded word.
 128
 129 Special Registers Altered:
 130
 131     None
 132
 133 # Load Floating-Point as Integer Word Zero Indexed Shifted
 134
 135 X-Form
 136
 137 * lfiwzsx FRT,RA,RB
 138
 139 Pseudo-code:
 140
 141     EA <- (RA|0) + (RB)<<(SH+1)
 142     FRT <- [0]*32 || MEM(EA, 4)
 143
 144 Description:
 145
 146     Let the effective address (EA) be the sum of (RA|0) with
 147     the contents of register RB shifted by (SH+1).
 148
 149     The word in storage addressed by EA is loaded into
 150     FRT [32:63]. FRT [0:31] are set to 0.
 151
 152 Special Registers Altered:
 153
 154     None