openpower/isa/fpstore.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.3 Floating-point store instructions. P 144 - 147 -->
   4
   5 # Store Floating-Point Single
   6
   7 D-Form
   8
   9 * stfs FRS,D(RA)
  10
  11 Pseudo-code:
  12
  13     EA <- (RA|0) + EXTS(D)
  14     MEM(EA, 4)<- SINGLE( (FRS) )
  15
  16 Description:
  17
  18     Let the effective address (EA) be the sum (RA|0)+D.
  19
  20     The contents of register FRS are converted to single
  21     format (see page 142) and stored into the word in stor-
  22     age addressed by EA.
  23
  24 Special Registers Altered:
  25
  26     None
  27
  28 # Store Floating-Point Single Indexed
  29
  30 X-Form
  31
  32 * stfsx FRS,RA,RB
  33
  34 Pseudo-code:
  35
  36     EA <- (RA|0) + (RB)
  37     MEM(EA, 4)<- SINGLE( (FRS) )
  38
  39 Description:
  40
  41     Let the effective address (EA) be the sum (RA|0)+(RB).
  42
  43     The contents of register FRS are converted to single
  44     format (see page 142) and stored into the word in stor-
  45     age addressed by EA.
  46
  47 Special Registers Altered:
  48
  49     None
  50
  51 # Store Floating-Point Single with Update
  52
  53 D-Form
  54
  55 * stfsu FRS,D(RA)
  56
  57 Pseudo-code:
  58
  59     EA <- (RA) + EXTS(D)
  60     MEM(EA, 4)<- SINGLE( (FRS) )
  61     RA <- EA
  62
  63 Description:
  64
  65     Let the effective address (EA) be the sum (RA) +D.
  66
  67     The contents of register FRS are converted to single
  68     format (see page 142) and stored into the word in stor-
  69     age addressed by EA.
  70
  71     EA is placed into register RA.
  72
  73     If RA=0, the instruction form is invalid.
  74
  75 Special Registers Altered:
  76
  77     None
  78
  79 # Store Floating-Point Single with Update Indexed
  80
  81 X-Form
  82
  83 * stfsux FRS,RA,RB
  84
  85 Pseudo-code:
  86
  87     EA <- (RA) + (RB)
  88     MEM(EA, 4)<- SINGLE( (FRS) )
  89     RA <- EA
  90
  91 Description:
  92
  93     Let the effective address (EA) be the sum (RA) +(RB).
  94
  95     The contents of register FRS are converted to single
  96     format (see page 142) and stored into the word in stor-
  97     age addressed by EA.
  98
  99     EA is placed into register RA.
 100
 101     If RA=0, the instruction form is invalid.
 102
 103 Special Registers Altered:
 104
 105     None
 106
 107 # Store Floating-Point Double
 108
 109 D-Form
 110
 111 * stfd FRS,D(RA)
 112
 113 Pseudo-code:
 114
 115     EA <- (RA|0) + EXTS(D)
 116     MEM(EA, 8)<- (FRS)
 117
 118 Description:
 119
 120     Let the effective address (EA) be the sum (RA|0)+D.
 121
 122     The contents of register FRS are stored into the dou-
 123     bleword in storage addressed by EA.
 124
 125 Special Registers Altered:
 126
 127     None
 128
 129 # Store Floating-Point Double Indexed
 130
 131 X-Form
 132
 133 * stfdx FRS,RA,RB
 134
 135 Pseudo-code:
 136
 137     EA <- (RA|0) + (RB)
 138     MEM(EA, 8)<- (FRS)
 139
 140 Description:
 141
 142     Let the effective address (EA) be the sum (RA|0)+(RB).
 143
 144     The contents of register FRS are stored into the dou-
 145     bleword in storage addressed by EA.
 146
 147 Special Registers Altered:
 148
 149     None
 150
 151 # Store Floating-Point Double with Update
 152
 153 D-Form
 154
 155 * stfdu FRS,D(RA)
 156
 157 Pseudo-code:
 158
 159     EA <- (RA) + EXTS(D)
 160     MEM(EA, 8)<- (FRS)
 161     RA <- EA
 162
 163 Description:
 164
 165     Let the effective address (EA) be the sum (RA)+D.
 166
 167     The contents of register FRS are stored into the dou-
 168     bleword in storage addressed by EA.
 169
 170     EA is placed into register RA.
 171
 172     If RA=0, the instruction form is invalid.
 173
 174 Special Registers Altered:
 175
 176     None
 177
 178 # Store Floating-Point Double with Update Indexed
 179
 180 X-Form
 181
 182 * stfdux FRS,RA,RB
 183
 184 Pseudo-code:
 185
 186     EA <- (RA) + (RB)
 187     MEM(EA, 8)<- (FRS)
 188     RA <- EA
 189
 190 Description:
 191
 192     Let the effective address (EA) be the sum (RA)+(RB).
 193
 194     The contents of register FRS are stored into the dou-
 195     bleword in storage addressed by EA.
 196
 197     EA is placed into register RA.
 198
 199     If RA=0, the instruction form is invalid.
 200
 201 Special Registers Altered:
 202
 203     None
 204
 205 # Store Floating-Point as Integer Word Indexed
 206
 207 X-Form
 208
 209 * stfiwx FRS,RA,RB
 210
 211 Pseudo-code:
 212
 213     b <- (RA|0)
 214     EA <- b + (RB)
 215     MEM(EA, 8)<- (FRS)[32:63]
 216
 217 Description:
 218
 219     Let the effective address (EA) be the sum (RA|0)+(RB).
 220
 221     (FRS)[32:63] are stored, without conversion, into the word
 222     in storage addressed by EA.
 223
 224     If the contents of register FRS were produced, either
 225     directly or indirectly, by a Load Floating-Point Single
 226     instruction, a single-precision Arithmetic instruction, or
 227     frsp, then the value stored is undefined. (The contents
 228     of register FRS are produced directly by such an
 229     instruction if FRS is the target register for the instruc-
 230     tion. The contents of register FRS are produced indi-
 231     rectly by such an instruction if FRS is the final target
 232     register of a sequence of one or more Floating-Point
 233     Move instructions, with the input to the sequence hav-
 234     ing been produced directly by such an instruction.)
 235
 236 Special Registers Altered:
 237
 238     None