openpower/isa/fptrans.mdwn

   1 <!-- Transcendental FP Instructions -->
   2
   3 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
   4
   5 # [DRAFT] Floating ATAN2 Single
   6
   7 X-Form
   8
   9 * fatan2s FRT,FRA,FRB (Rc=0)
  10 * fatan2s. FRT,FRA,FRB (Rc=1)
  11
  12 Pseudo-code:
  13
  14     FRT <- DOUBLE(bfp32_ATAN2(SINGLE(FRA), SINGLE(FRB)))
  15
  16 Special Registers Altered:
  17
  18     FPRF FR FI
  19     FX OX UX XX
  20     VXSNAN VXISI VXIMZ
  21     CR1          (if Rc=1)
  22
  23 # [DRAFT] Floating ATAN2
  24
  25 X-Form
  26
  27 * fatan2 FRT,FRA,FRB (Rc=0)
  28 * fatan2. FRT,FRA,FRB (Rc=1)
  29
  30 Pseudo-code:
  31
  32     FRT <- bfp64_ATAN2(FRA, FRB)
  33
  34 Special Registers Altered:
  35
  36     FPRF FR FI
  37     FX OX UX XX
  38     VXSNAN VXISI VXIMZ
  39     CR1          (if Rc=1)
  40
  41 # [DRAFT] Floating ATAN2PI Single
  42
  43 X-Form
  44
  45 * fatan2pis FRT,FRA,FRB (Rc=0)
  46 * fatan2pis. FRT,FRA,FRB (Rc=1)
  47
  48 Pseudo-code:
  49
  50     FRT <- DOUBLE(bfp32_ATAN2PI(SINGLE(FRA), SINGLE(FRB)))
  51
  52 Special Registers Altered:
  53
  54     FPRF FR FI
  55     FX OX UX XX
  56     VXSNAN VXISI VXIMZ
  57     CR1          (if Rc=1)
  58
  59 # [DRAFT] Floating ATAN2PI
  60
  61 X-Form
  62
  63 * fatan2pi FRT,FRA,FRB (Rc=0)
  64 * fatan2pi. FRT,FRA,FRB (Rc=1)
  65
  66 Pseudo-code:
  67
  68     FRT <- bfp64_ATAN2PI(FRA, FRB)
  69
  70 Special Registers Altered:
  71
  72     FPRF FR FI
  73     FX OX UX XX
  74     VXSNAN VXISI VXIMZ
  75     CR1          (if Rc=1)
  76
  77 # [DRAFT] Floating POW Single
  78
  79 X-Form
  80
  81 * fpows FRT,FRA,FRB (Rc=0)
  82 * fpows. FRT,FRA,FRB (Rc=1)
  83
  84 Pseudo-code:
  85
  86     FRT <- DOUBLE(bfp32_POW(SINGLE(FRA), SINGLE(FRB)))
  87
  88 Special Registers Altered:
  89
  90     FPRF FR FI
  91     FX OX UX XX
  92     VXSNAN VXISI VXIMZ
  93     CR1          (if Rc=1)
  94
  95 # [DRAFT] Floating POW
  96
  97 X-Form
  98
  99 * fpow FRT,FRA,FRB (Rc=0)
 100 * fpow. FRT,FRA,FRB (Rc=1)
 101
 102 Pseudo-code:
 103
 104     FRT <- bfp64_POW(FRA, FRB)
 105
 106 Special Registers Altered:
 107
 108     FPRF FR FI
 109     FX OX UX XX
 110     VXSNAN VXISI VXIMZ
 111     CR1          (if Rc=1)
 112
 113 # [DRAFT] Floating POWN Single
 114
 115 X-Form
 116
 117 * fpowns FRT,FRA,RB (Rc=0)
 118 * fpowns. FRT,FRA,RB (Rc=1)
 119
 120 Pseudo-code:
 121
 122     FRT <- DOUBLE(bfp32_POWN(SINGLE(FRA), RB))
 123
 124 Special Registers Altered:
 125
 126     FPRF FR FI
 127     FX OX UX XX
 128     VXSNAN VXISI VXIMZ
 129     CR1          (if Rc=1)
 130
 131 # [DRAFT] Floating POWN
 132
 133 X-Form
 134
 135 * fpown FRT,FRA,RB (Rc=0)
 136 * fpown. FRT,FRA,RB (Rc=1)
 137
 138 Pseudo-code:
 139
 140     FRT <- bfp64_POWN(FRA, RB)
 141
 142 Special Registers Altered:
 143
 144     FPRF FR FI
 145     FX OX UX XX
 146     VXSNAN VXISI VXIMZ
 147     CR1          (if Rc=1)
 148
 149 # [DRAFT] Floating POWR Single
 150
 151 X-Form
 152
 153 * fpowrs FRT,FRA,FRB (Rc=0)
 154 * fpowrs. FRT,FRA,FRB (Rc=1)
 155
 156 Pseudo-code:
 157
 158     FRT <- DOUBLE(bfp32_POWR(SINGLE(FRA), SINGLE(FRB)))
 159
 160 Special Registers Altered:
 161
 162     FPRF FR FI
 163     FX OX UX XX
 164     VXSNAN VXISI VXIMZ
 165     CR1          (if Rc=1)
 166
 167 # [DRAFT] Floating POWR
 168
 169 X-Form
 170
 171 * fpowr FRT,FRA,FRB (Rc=0)
 172 * fpowr. FRT,FRA,FRB (Rc=1)
 173
 174 Pseudo-code:
 175
 176     FRT <- bfp64_POWR(FRA, FRB)
 177
 178 Special Registers Altered:
 179
 180     FPRF FR FI
 181     FX OX UX XX
 182     VXSNAN VXISI VXIMZ
 183     CR1          (if Rc=1)
 184
 185 # [DRAFT] Floating ROOTN Single
 186
 187 X-Form
 188
 189 * frootns FRT,FRA,RB (Rc=0)
 190 * frootns. FRT,FRA,RB (Rc=1)
 191
 192 Pseudo-code:
 193
 194     FRT <- DOUBLE(bfp32_ROOTN(SINGLE(FRA), RB))
 195
 196 Special Registers Altered:
 197
 198     FPRF FR FI
 199     FX OX UX XX
 200     VXSNAN VXISI VXIMZ
 201     CR1          (if Rc=1)
 202
 203 # [DRAFT] Floating ROOTN
 204
 205 X-Form
 206
 207 * frootn FRT,FRA,RB (Rc=0)
 208 * frootn. FRT,FRA,RB (Rc=1)
 209
 210 Pseudo-code:
 211
 212     FRT <- bfp64_ROOTN(FRA, RB)
 213
 214 Special Registers Altered:
 215
 216     FPRF FR FI
 217     FX OX UX XX
 218     VXSNAN VXISI VXIMZ
 219     CR1          (if Rc=1)
 220
 221 # [DRAFT] Floating HYPOT Single
 222
 223 X-Form
 224
 225 * fhypots FRT,FRA,FRB (Rc=0)
 226 * fhypots. FRT,FRA,FRB (Rc=1)
 227
 228 Pseudo-code:
 229
 230     FRT <- DOUBLE(bfp32_HYPOT(SINGLE(FRA), SINGLE(FRB)))
 231
 232 Special Registers Altered:
 233
 234     FPRF FR FI
 235     FX OX UX XX
 236     VXSNAN VXISI VXIMZ
 237     CR1          (if Rc=1)
 238
 239 # [DRAFT] Floating HYPOT
 240
 241 X-Form
 242
 243 * fhypot FRT,FRA,FRB (Rc=0)
 244 * fhypot. FRT,FRA,FRB (Rc=1)
 245
 246 Pseudo-code:
 247
 248     FRT <- bfp64_HYPOT(FRA, FRB)
 249
 250 Special Registers Altered:
 251
 252     FPRF FR FI
 253     FX OX UX XX
 254     VXSNAN VXISI VXIMZ
 255     CR1          (if Rc=1)
 256
 257 # [DRAFT] Floating RSQRT Single
 258
 259 X-Form
 260
 261 * frsqrts FRT,FRB (Rc=0)
 262 * frsqrts. FRT,FRB (Rc=1)
 263
 264 Pseudo-code:
 265
 266     FRT <- DOUBLE(bfp32_RSQRT(SINGLE(FRB)))
 267
 268 Special Registers Altered:
 269
 270     FPRF FR FI
 271     FX OX UX XX
 272     VXSNAN VXISI VXIMZ
 273     CR1          (if Rc=1)
 274
 275 # [DRAFT] Floating RSQRT
 276
 277 X-Form
 278
 279 * frsqrt FRT,FRB (Rc=0)
 280 * frsqrt. FRT,FRB (Rc=1)
 281
 282 Pseudo-code:
 283
 284     FRT <- bfp64_RSQRT(FRB)
 285
 286 Special Registers Altered:
 287
 288     FPRF FR FI
 289     FX OX UX XX
 290     VXSNAN VXISI VXIMZ
 291     CR1          (if Rc=1)
 292
 293 # [DRAFT] Floating CBRT Single
 294
 295 X-Form
 296
 297 * fcbrts FRT,FRB (Rc=0)
 298 * fcbrts. FRT,FRB (Rc=1)
 299
 300 Pseudo-code:
 301
 302     FRT <- DOUBLE(bfp32_CBRT(SINGLE(FRB)))
 303
 304 Special Registers Altered:
 305
 306     FPRF FR FI
 307     FX OX UX XX
 308     VXSNAN VXISI VXIMZ
 309     CR1          (if Rc=1)
 310
 311 # [DRAFT] Floating CBRT
 312
 313 X-Form
 314
 315 * fcbrt FRT,FRB (Rc=0)
 316 * fcbrt. FRT,FRB (Rc=1)
 317
 318 Pseudo-code:
 319
 320     FRT <- bfp64_CBRT(FRB)
 321
 322 Special Registers Altered:
 323
 324     FPRF FR FI
 325     FX OX UX XX
 326     VXSNAN VXISI VXIMZ
 327     CR1          (if Rc=1)
 328
 329 # [DRAFT] Floating RECIP Single
 330
 331 X-Form
 332
 333 * frecips FRT,FRB (Rc=0)
 334 * frecips. FRT,FRB (Rc=1)
 335
 336 Pseudo-code:
 337
 338     FRT <- DOUBLE(bfp32_RECIP(SINGLE(FRB)))
 339
 340 Special Registers Altered:
 341
 342     FPRF FR FI
 343     FX OX UX XX
 344     VXSNAN VXISI VXIMZ
 345     CR1          (if Rc=1)
 346
 347 # [DRAFT] Floating RECIP
 348
 349 X-Form
 350
 351 * frecip FRT,FRB (Rc=0)
 352 * frecip. FRT,FRB (Rc=1)
 353
 354 Pseudo-code:
 355
 356     FRT <- bfp64_RECIP(FRB)
 357
 358 Special Registers Altered:
 359
 360     FPRF FR FI
 361     FX OX UX XX
 362     VXSNAN VXISI VXIMZ
 363     CR1          (if Rc=1)
 364
 365 # [DRAFT] Floating EXP2M1 Single
 366
 367 X-Form
 368
 369 * fexp2m1s FRT,FRB (Rc=0)
 370 * fexp2m1s. FRT,FRB (Rc=1)
 371
 372 Pseudo-code:
 373
 374     FRT <- DOUBLE(bfp32_EXP2M1(SINGLE(FRB)))
 375
 376 Special Registers Altered:
 377
 378     FPRF FR FI
 379     FX OX UX XX
 380     VXSNAN VXISI VXIMZ
 381     CR1          (if Rc=1)
 382
 383 # [DRAFT] Floating EXP2M1
 384
 385 X-Form
 386
 387 * fexp2m1 FRT,FRB (Rc=0)
 388 * fexp2m1. FRT,FRB (Rc=1)
 389
 390 Pseudo-code:
 391
 392     FRT <- bfp64_EXP2M1(FRB)
 393
 394 Special Registers Altered:
 395
 396     FPRF FR FI
 397     FX OX UX XX
 398     VXSNAN VXISI VXIMZ
 399     CR1          (if Rc=1)
 400
 401 # [DRAFT] Floating LOG2P1 Single
 402
 403 X-Form
 404
 405 * flog2p1s FRT,FRB (Rc=0)
 406 * flog2p1s. FRT,FRB (Rc=1)
 407
 408 Pseudo-code:
 409
 410     FRT <- DOUBLE(bfp32_LOG2P1(SINGLE(FRB)))
 411
 412 Special Registers Altered:
 413
 414     FPRF FR FI
 415     FX OX UX XX
 416     VXSNAN VXISI VXIMZ
 417     CR1          (if Rc=1)
 418
 419 # [DRAFT] Floating LOG2P1
 420
 421 X-Form
 422
 423 * flog2p1 FRT,FRB (Rc=0)
 424 * flog2p1. FRT,FRB (Rc=1)
 425
 426 Pseudo-code:
 427
 428     FRT <- bfp64_LOG2P1(FRB)
 429
 430 Special Registers Altered:
 431
 432     FPRF FR FI
 433     FX OX UX XX
 434     VXSNAN VXISI VXIMZ
 435     CR1          (if Rc=1)
 436
 437 # [DRAFT] Floating EXP2 Single
 438
 439 X-Form
 440
 441 * fexp2s FRT,FRB (Rc=0)
 442 * fexp2s. FRT,FRB (Rc=1)
 443
 444 Pseudo-code:
 445
 446     FRT <- DOUBLE(bfp32_EXP2(SINGLE(FRB)))
 447
 448 Special Registers Altered:
 449
 450     FPRF FR FI
 451     FX OX UX XX
 452     VXSNAN VXISI VXIMZ
 453     CR1          (if Rc=1)
 454
 455 # [DRAFT] Floating EXP2
 456
 457 X-Form
 458
 459 * fexp2 FRT,FRB (Rc=0)
 460 * fexp2. FRT,FRB (Rc=1)
 461
 462 Pseudo-code:
 463
 464     FRT <- bfp64_EXP2(FRB)
 465
 466 Special Registers Altered:
 467
 468     FPRF FR FI
 469     FX OX UX XX
 470     VXSNAN VXISI VXIMZ
 471     CR1          (if Rc=1)
 472
 473 # [DRAFT] Floating LOG2 Single
 474
 475 X-Form
 476
 477 * flog2s FRT,FRB (Rc=0)
 478 * flog2s. FRT,FRB (Rc=1)
 479
 480 Pseudo-code:
 481
 482     FRT <- DOUBLE(bfp32_LOG2(SINGLE(FRB)))
 483
 484 Special Registers Altered:
 485
 486     FPRF FR FI
 487     FX OX UX XX
 488     VXSNAN VXISI VXIMZ
 489     CR1          (if Rc=1)
 490
 491 # [DRAFT] Floating LOG2
 492
 493 X-Form
 494
 495 * flog2 FRT,FRB (Rc=0)
 496 * flog2. FRT,FRB (Rc=1)
 497
 498 Pseudo-code:
 499
 500     FRT <- bfp64_LOG2(FRB)
 501
 502 Special Registers Altered:
 503
 504     FPRF FR FI
 505     FX OX UX XX
 506     VXSNAN VXISI VXIMZ
 507     CR1          (if Rc=1)
 508
 509 # [DRAFT] Floating EXPM1 Single
 510
 511 X-Form
 512
 513 * fexpm1s FRT,FRB (Rc=0)
 514 * fexpm1s. FRT,FRB (Rc=1)
 515
 516 Pseudo-code:
 517
 518     FRT <- DOUBLE(bfp32_EXPM1(SINGLE(FRB)))
 519
 520 Special Registers Altered:
 521
 522     FPRF FR FI
 523     FX OX UX XX
 524     VXSNAN VXISI VXIMZ
 525     CR1          (if Rc=1)
 526
 527 # [DRAFT] Floating EXPM1
 528
 529 X-Form
 530
 531 * fexpm1 FRT,FRB (Rc=0)
 532 * fexpm1. FRT,FRB (Rc=1)
 533
 534 Pseudo-code:
 535
 536     FRT <- bfp64_EXPM1(FRB)
 537
 538 Special Registers Altered:
 539
 540     FPRF FR FI
 541     FX OX UX XX
 542     VXSNAN VXISI VXIMZ
 543     CR1          (if Rc=1)
 544
 545 # [DRAFT] Floating LOGP1 Single
 546
 547 X-Form
 548
 549 * flogp1s FRT,FRB (Rc=0)
 550 * flogp1s. FRT,FRB (Rc=1)
 551
 552 Pseudo-code:
 553
 554     FRT <- DOUBLE(bfp32_LOGP1(SINGLE(FRB)))
 555
 556 Special Registers Altered:
 557
 558     FPRF FR FI
 559     FX OX UX XX
 560     VXSNAN VXISI VXIMZ
 561     CR1          (if Rc=1)
 562
 563 # [DRAFT] Floating LOGP1
 564
 565 X-Form
 566
 567 * flogp1 FRT,FRB (Rc=0)
 568 * flogp1. FRT,FRB (Rc=1)
 569
 570 Pseudo-code:
 571
 572     FRT <- bfp64_LOGP1(FRB)
 573
 574 Special Registers Altered:
 575
 576     FPRF FR FI
 577     FX OX UX XX
 578     VXSNAN VXISI VXIMZ
 579     CR1          (if Rc=1)
 580
 581 # [DRAFT] Floating EXP Single
 582
 583 X-Form
 584
 585 * fexps FRT,FRB (Rc=0)
 586 * fexps. FRT,FRB (Rc=1)
 587
 588 Pseudo-code:
 589
 590     FRT <- DOUBLE(bfp32_EXP(SINGLE(FRB)))
 591
 592 Special Registers Altered:
 593
 594     FPRF FR FI
 595     FX OX UX XX
 596     VXSNAN VXISI VXIMZ
 597     CR1          (if Rc=1)
 598
 599 # [DRAFT] Floating EXP
 600
 601 X-Form
 602
 603 * fexp FRT,FRB (Rc=0)
 604 * fexp. FRT,FRB (Rc=1)
 605
 606 Pseudo-code:
 607
 608     FRT <- bfp64_EXP(FRB)
 609
 610 Special Registers Altered:
 611
 612     FPRF FR FI
 613     FX OX UX XX
 614     VXSNAN VXISI VXIMZ
 615     CR1          (if Rc=1)
 616
 617 # [DRAFT] Floating LOG Single
 618
 619 X-Form
 620
 621 * flogs FRT,FRB (Rc=0)
 622 * flogs. FRT,FRB (Rc=1)
 623
 624 Pseudo-code:
 625
 626     FRT <- DOUBLE(bfp32_LOG(SINGLE(FRB)))
 627
 628 Special Registers Altered:
 629
 630     FPRF FR FI
 631     FX OX UX XX
 632     VXSNAN VXISI VXIMZ
 633     CR1          (if Rc=1)
 634
 635 # [DRAFT] Floating LOG
 636
 637 X-Form
 638
 639 * flog FRT,FRB (Rc=0)
 640 * flog. FRT,FRB (Rc=1)
 641
 642 Pseudo-code:
 643
 644     FRT <- bfp64_LOG(FRB)
 645
 646 Special Registers Altered:
 647
 648     FPRF FR FI
 649     FX OX UX XX
 650     VXSNAN VXISI VXIMZ
 651     CR1          (if Rc=1)
 652
 653 # [DRAFT] Floating EXP10M1 Single
 654
 655 X-Form
 656
 657 * fexp10m1s FRT,FRB (Rc=0)
 658 * fexp10m1s. FRT,FRB (Rc=1)
 659
 660 Pseudo-code:
 661
 662     FRT <- DOUBLE(bfp32_EXP10M1(SINGLE(FRB)))
 663
 664 Special Registers Altered:
 665
 666     FPRF FR FI
 667     FX OX UX XX
 668     VXSNAN VXISI VXIMZ
 669     CR1          (if Rc=1)
 670
 671 # [DRAFT] Floating EXP10M1
 672
 673 X-Form
 674
 675 * fexp10m1 FRT,FRB (Rc=0)
 676 * fexp10m1. FRT,FRB (Rc=1)
 677
 678 Pseudo-code:
 679
 680     FRT <- bfp64_EXP10M1(FRB)
 681
 682 Special Registers Altered:
 683
 684     FPRF FR FI
 685     FX OX UX XX
 686     VXSNAN VXISI VXIMZ
 687     CR1          (if Rc=1)
 688
 689 # [DRAFT] Floating LOG10P1 Single
 690
 691 X-Form
 692
 693 * flog10p1s FRT,FRB (Rc=0)
 694 * flog10p1s. FRT,FRB (Rc=1)
 695
 696 Pseudo-code:
 697
 698     FRT <- DOUBLE(bfp32_LOG10P1(SINGLE(FRB)))
 699
 700 Special Registers Altered:
 701
 702     FPRF FR FI
 703     FX OX UX XX
 704     VXSNAN VXISI VXIMZ
 705     CR1          (if Rc=1)
 706
 707 # [DRAFT] Floating LOG10P1
 708
 709 X-Form
 710
 711 * flog10p1 FRT,FRB (Rc=0)
 712 * flog10p1. FRT,FRB (Rc=1)
 713
 714 Pseudo-code:
 715
 716     FRT <- bfp64_LOG10P1(FRB)
 717
 718 Special Registers Altered:
 719
 720     FPRF FR FI
 721     FX OX UX XX
 722     VXSNAN VXISI VXIMZ
 723     CR1          (if Rc=1)
 724
 725 # [DRAFT] Floating EXP10 Single
 726
 727 X-Form
 728
 729 * fexp10s FRT,FRB (Rc=0)
 730 * fexp10s. FRT,FRB (Rc=1)
 731
 732 Pseudo-code:
 733
 734     FRT <- DOUBLE(bfp32_EXP10(SINGLE(FRB)))
 735
 736 Special Registers Altered:
 737
 738     FPRF FR FI
 739     FX OX UX XX
 740     VXSNAN VXISI VXIMZ
 741     CR1          (if Rc=1)
 742
 743 # [DRAFT] Floating EXP10
 744
 745 X-Form
 746
 747 * fexp10 FRT,FRB (Rc=0)
 748 * fexp10. FRT,FRB (Rc=1)
 749
 750 Pseudo-code:
 751
 752     FRT <- bfp64_EXP10(FRB)
 753
 754 Special Registers Altered:
 755
 756     FPRF FR FI
 757     FX OX UX XX
 758     VXSNAN VXISI VXIMZ
 759     CR1          (if Rc=1)
 760
 761 # [DRAFT] Floating LOG10 Single
 762
 763 X-Form
 764
 765 * flog10s FRT,FRB (Rc=0)
 766 * flog10s. FRT,FRB (Rc=1)
 767
 768 Pseudo-code:
 769
 770     FRT <- DOUBLE(bfp32_LOG10(SINGLE(FRB)))
 771
 772 Special Registers Altered:
 773
 774     FPRF FR FI
 775     FX OX UX XX
 776     VXSNAN VXISI VXIMZ
 777     CR1          (if Rc=1)
 778
 779 # [DRAFT] Floating LOG10
 780
 781 X-Form
 782
 783 * flog10 FRT,FRB (Rc=0)
 784 * flog10. FRT,FRB (Rc=1)
 785
 786 Pseudo-code:
 787
 788     FRT <- bfp64_LOG10(FRB)
 789
 790 Special Registers Altered:
 791
 792     FPRF FR FI
 793     FX OX UX XX
 794     VXSNAN VXISI VXIMZ
 795     CR1          (if Rc=1)
 796
 797 # [DRAFT] Floating SIN Single
 798
 799 X-Form
 800
 801 * fsins FRT,FRB (Rc=0)
 802 * fsins. FRT,FRB (Rc=1)
 803
 804 Pseudo-code:
 805
 806     FRT <- DOUBLE(bfp32_SIN(SINGLE(FRB)))
 807
 808 Special Registers Altered:
 809
 810     FPRF FR FI
 811     FX OX UX XX
 812     VXSNAN VXISI VXIMZ
 813     CR1          (if Rc=1)
 814
 815 # [DRAFT] Floating SIN
 816
 817 X-Form
 818
 819 * fsin FRT,FRB (Rc=0)
 820 * fsin. FRT,FRB (Rc=1)
 821
 822 Pseudo-code:
 823
 824     FRT <- bfp64_SIN(FRB)
 825
 826 Special Registers Altered:
 827
 828     FPRF FR FI
 829     FX OX UX XX
 830     VXSNAN VXISI VXIMZ
 831     CR1          (if Rc=1)
 832
 833 # [DRAFT] Floating COS Single
 834
 835 X-Form
 836
 837 * fcoss FRT,FRB (Rc=0)
 838 * fcoss. FRT,FRB (Rc=1)
 839
 840 Pseudo-code:
 841
 842     FRT <- DOUBLE(bfp32_COS(SINGLE(FRB)))
 843
 844 Special Registers Altered:
 845
 846     FPRF FR FI
 847     FX OX UX XX
 848     VXSNAN VXISI VXIMZ
 849     CR1          (if Rc=1)
 850
 851 # [DRAFT] Floating COS
 852
 853 X-Form
 854
 855 * fcos FRT,FRB (Rc=0)
 856 * fcos. FRT,FRB (Rc=1)
 857
 858 Pseudo-code:
 859
 860     FRT <- bfp64_COS(FRB)
 861
 862 Special Registers Altered:
 863
 864     FPRF FR FI
 865     FX OX UX XX
 866     VXSNAN VXISI VXIMZ
 867     CR1          (if Rc=1)
 868
 869 # [DRAFT] Floating TAN Single
 870
 871 X-Form
 872
 873 * ftans FRT,FRB (Rc=0)
 874 * ftans. FRT,FRB (Rc=1)
 875
 876 Pseudo-code:
 877
 878     FRT <- DOUBLE(bfp32_TAN(SINGLE(FRB)))
 879
 880 Special Registers Altered:
 881
 882     FPRF FR FI
 883     FX OX UX XX
 884     VXSNAN VXISI VXIMZ
 885     CR1          (if Rc=1)
 886
 887 # [DRAFT] Floating TAN
 888
 889 X-Form
 890
 891 * ftan FRT,FRB (Rc=0)
 892 * ftan. FRT,FRB (Rc=1)
 893
 894 Pseudo-code:
 895
 896     FRT <- bfp64_TAN(FRB)
 897
 898 Special Registers Altered:
 899
 900     FPRF FR FI
 901     FX OX UX XX
 902     VXSNAN VXISI VXIMZ
 903     CR1          (if Rc=1)
 904
 905 # [DRAFT] Floating ASIN Single
 906
 907 X-Form
 908
 909 * fasins FRT,FRB (Rc=0)
 910 * fasins. FRT,FRB (Rc=1)
 911
 912 Pseudo-code:
 913
 914     FRT <- DOUBLE(bfp32_ASIN(SINGLE(FRB)))
 915
 916 Special Registers Altered:
 917
 918     FPRF FR FI
 919     FX OX UX XX
 920     VXSNAN VXISI VXIMZ
 921     CR1          (if Rc=1)
 922
 923 # [DRAFT] Floating ASIN
 924
 925 X-Form
 926
 927 * fasin FRT,FRB (Rc=0)
 928 * fasin. FRT,FRB (Rc=1)
 929
 930 Pseudo-code:
 931
 932     FRT <- bfp64_ASIN(FRB)
 933
 934 Special Registers Altered:
 935
 936     FPRF FR FI
 937     FX OX UX XX
 938     VXSNAN VXISI VXIMZ
 939     CR1          (if Rc=1)
 940
 941 # [DRAFT] Floating ACOS Single
 942
 943 X-Form
 944
 945 * facoss FRT,FRB (Rc=0)
 946 * facoss. FRT,FRB (Rc=1)
 947
 948 Pseudo-code:
 949
 950     FRT <- DOUBLE(bfp32_ACOS(SINGLE(FRB)))
 951
 952 Special Registers Altered:
 953
 954     FPRF FR FI
 955     FX OX UX XX
 956     VXSNAN VXISI VXIMZ
 957     CR1          (if Rc=1)
 958
 959 # [DRAFT] Floating ACOS
 960
 961 X-Form
 962
 963 * facos FRT,FRB (Rc=0)
 964 * facos. FRT,FRB (Rc=1)
 965
 966 Pseudo-code:
 967
 968     FRT <- bfp64_ACOS(FRB)
 969
 970 Special Registers Altered:
 971
 972     FPRF FR FI
 973     FX OX UX XX
 974     VXSNAN VXISI VXIMZ
 975     CR1          (if Rc=1)
 976
 977 # [DRAFT] Floating ATAN Single
 978
 979 X-Form
 980
 981 * fatans FRT,FRB (Rc=0)
 982 * fatans. FRT,FRB (Rc=1)
 983
 984 Pseudo-code:
 985
 986     FRT <- DOUBLE(bfp32_ATAN(SINGLE(FRB)))
 987
 988 Special Registers Altered:
 989
 990     FPRF FR FI
 991     FX OX UX XX
 992     VXSNAN VXISI VXIMZ
 993     CR1          (if Rc=1)
 994
 995 # [DRAFT] Floating ATAN
 996
 997 X-Form
 998
 999 * fatan FRT,FRB (Rc=0)
1000 * fatan. FRT,FRB (Rc=1)
1001
1002 Pseudo-code:
1003
1004     FRT <- bfp64_ATAN(FRB)
1005
1006 Special Registers Altered:
1007
1008     FPRF FR FI
1009     FX OX UX XX
1010     VXSNAN VXISI VXIMZ
1011     CR1          (if Rc=1)
1012
1013 # [DRAFT] Floating SINPI Single
1014
1015 X-Form
1016
1017 * fsinpis FRT,FRB (Rc=0)
1018 * fsinpis. FRT,FRB (Rc=1)
1019
1020 Pseudo-code:
1021
1022     FRT <- DOUBLE(bfp32_SINPI(SINGLE(FRB)))
1023
1024 Special Registers Altered:
1025
1026     FPRF FR FI
1027     FX OX UX XX
1028     VXSNAN VXISI VXIMZ
1029     CR1          (if Rc=1)
1030
1031 # [DRAFT] Floating SINPI
1032
1033 X-Form
1034
1035 * fsinpi FRT,FRB (Rc=0)
1036 * fsinpi. FRT,FRB (Rc=1)
1037
1038 Pseudo-code:
1039
1040     FRT <- bfp64_SINPI(FRB)
1041
1042 Special Registers Altered:
1043
1044     FPRF FR FI
1045     FX OX UX XX
1046     VXSNAN VXISI VXIMZ
1047     CR1          (if Rc=1)
1048
1049 # [DRAFT] Floating COSPI Single
1050
1051 X-Form
1052
1053 * fcospis FRT,FRB (Rc=0)
1054 * fcospis. FRT,FRB (Rc=1)
1055
1056 Pseudo-code:
1057
1058     FRT <- DOUBLE(bfp32_COSPI(SINGLE(FRB)))
1059
1060 Special Registers Altered:
1061
1062     FPRF FR FI
1063     FX OX UX XX
1064     VXSNAN VXISI VXIMZ
1065     CR1          (if Rc=1)
1066
1067 # [DRAFT] Floating COSPI
1068
1069 X-Form
1070
1071 * fcospi FRT,FRB (Rc=0)
1072 * fcospi. FRT,FRB (Rc=1)
1073
1074 Pseudo-code:
1075
1076     FRT <- bfp64_COSPI(FRB)
1077
1078 Special Registers Altered:
1079
1080     FPRF FR FI
1081     FX OX UX XX
1082     VXSNAN VXISI VXIMZ
1083     CR1          (if Rc=1)
1084
1085 # [DRAFT] Floating TANPI Single
1086
1087 X-Form
1088
1089 * ftanpis FRT,FRB (Rc=0)
1090 * ftanpis. FRT,FRB (Rc=1)
1091
1092 Pseudo-code:
1093
1094     FRT <- DOUBLE(bfp32_TANPI(SINGLE(FRB)))
1095
1096 Special Registers Altered:
1097
1098     FPRF FR FI
1099     FX OX UX XX
1100     VXSNAN VXISI VXIMZ
1101     CR1          (if Rc=1)
1102
1103 # [DRAFT] Floating TANPI
1104
1105 X-Form
1106
1107 * ftanpi FRT,FRB (Rc=0)
1108 * ftanpi. FRT,FRB (Rc=1)
1109
1110 Pseudo-code:
1111
1112     FRT <- bfp64_TANPI(FRB)
1113
1114 Special Registers Altered:
1115
1116     FPRF FR FI
1117     FX OX UX XX
1118     VXSNAN VXISI VXIMZ
1119     CR1          (if Rc=1)
1120
1121 # [DRAFT] Floating ASINPI Single
1122
1123 X-Form
1124
1125 * fasinpis FRT,FRB (Rc=0)
1126 * fasinpis. FRT,FRB (Rc=1)
1127
1128 Pseudo-code:
1129
1130     FRT <- DOUBLE(bfp32_ASINPI(SINGLE(FRB)))
1131
1132 Special Registers Altered:
1133
1134     FPRF FR FI
1135     FX OX UX XX
1136     VXSNAN VXISI VXIMZ
1137     CR1          (if Rc=1)
1138
1139 # [DRAFT] Floating ASINPI
1140
1141 X-Form
1142
1143 * fasinpi FRT,FRB (Rc=0)
1144 * fasinpi. FRT,FRB (Rc=1)
1145
1146 Pseudo-code:
1147
1148     FRT <- bfp64_ASINPI(FRB)
1149
1150 Special Registers Altered:
1151
1152     FPRF FR FI
1153     FX OX UX XX
1154     VXSNAN VXISI VXIMZ
1155     CR1          (if Rc=1)
1156
1157 # [DRAFT] Floating ACOSPI Single
1158
1159 X-Form
1160
1161 * facospis FRT,FRB (Rc=0)
1162 * facospis. FRT,FRB (Rc=1)
1163
1164 Pseudo-code:
1165
1166     FRT <- DOUBLE(bfp32_ACOSPI(SINGLE(FRB)))
1167
1168 Special Registers Altered:
1169
1170     FPRF FR FI
1171     FX OX UX XX
1172     VXSNAN VXISI VXIMZ
1173     CR1          (if Rc=1)
1174
1175 # [DRAFT] Floating ACOSPI
1176
1177 X-Form
1178
1179 * facospi FRT,FRB (Rc=0)
1180 * facospi. FRT,FRB (Rc=1)
1181
1182 Pseudo-code:
1183
1184     FRT <- bfp64_ACOSPI(FRB)
1185
1186 Special Registers Altered:
1187
1188     FPRF FR FI
1189     FX OX UX XX
1190     VXSNAN VXISI VXIMZ
1191     CR1          (if Rc=1)
1192
1193 # [DRAFT] Floating ATANPI Single
1194
1195 X-Form
1196
1197 * fatanpis FRT,FRB (Rc=0)
1198 * fatanpis. FRT,FRB (Rc=1)
1199
1200 Pseudo-code:
1201
1202     FRT <- DOUBLE(bfp32_ATANPI(SINGLE(FRB)))
1203
1204 Special Registers Altered:
1205
1206     FPRF FR FI
1207     FX OX UX XX
1208     VXSNAN VXISI VXIMZ
1209     CR1          (if Rc=1)
1210
1211 # [DRAFT] Floating ATANPI
1212
1213 X-Form
1214
1215 * fatanpi FRT,FRB (Rc=0)
1216 * fatanpi. FRT,FRB (Rc=1)
1217
1218 Pseudo-code:
1219
1220     FRT <- bfp64_ATANPI(FRB)
1221
1222 Special Registers Altered:
1223
1224     FPRF FR FI
1225     FX OX UX XX
1226     VXSNAN VXISI VXIMZ
1227     CR1          (if Rc=1)
1228
1229 # [DRAFT] Floating SINH Single
1230
1231 X-Form
1232
1233 * fsinhs FRT,FRB (Rc=0)
1234 * fsinhs. FRT,FRB (Rc=1)
1235
1236 Pseudo-code:
1237
1238     FRT <- DOUBLE(bfp32_SINH(SINGLE(FRB)))
1239
1240 Special Registers Altered:
1241
1242     FPRF FR FI
1243     FX OX UX XX
1244     VXSNAN VXISI VXIMZ
1245     CR1          (if Rc=1)
1246
1247 # [DRAFT] Floating SINH
1248
1249 X-Form
1250
1251 * fsinh FRT,FRB (Rc=0)
1252 * fsinh. FRT,FRB (Rc=1)
1253
1254 Pseudo-code:
1255
1256     FRT <- bfp64_SINH(FRB)
1257
1258 Special Registers Altered:
1259
1260     FPRF FR FI
1261     FX OX UX XX
1262     VXSNAN VXISI VXIMZ
1263     CR1          (if Rc=1)
1264
1265 # [DRAFT] Floating COSH Single
1266
1267 X-Form
1268
1269 * fcoshs FRT,FRB (Rc=0)
1270 * fcoshs. FRT,FRB (Rc=1)
1271
1272 Pseudo-code:
1273
1274     FRT <- DOUBLE(bfp32_COSH(SINGLE(FRB)))
1275
1276 Special Registers Altered:
1277
1278     FPRF FR FI
1279     FX OX UX XX
1280     VXSNAN VXISI VXIMZ
1281     CR1          (if Rc=1)
1282
1283 # [DRAFT] Floating COSH
1284
1285 X-Form
1286
1287 * fcosh FRT,FRB (Rc=0)
1288 * fcosh. FRT,FRB (Rc=1)
1289
1290 Pseudo-code:
1291
1292     FRT <- bfp64_COSH(FRB)
1293
1294 Special Registers Altered:
1295
1296     FPRF FR FI
1297     FX OX UX XX
1298     VXSNAN VXISI VXIMZ
1299     CR1          (if Rc=1)
1300
1301 # [DRAFT] Floating TANH Single
1302
1303 X-Form
1304
1305 * ftanhs FRT,FRB (Rc=0)
1306 * ftanhs. FRT,FRB (Rc=1)
1307
1308 Pseudo-code:
1309
1310     FRT <- DOUBLE(bfp32_TANH(SINGLE(FRB)))
1311
1312 Special Registers Altered:
1313
1314     FPRF FR FI
1315     FX OX UX XX
1316     VXSNAN VXISI VXIMZ
1317     CR1          (if Rc=1)
1318
1319 # [DRAFT] Floating TANH
1320
1321 X-Form
1322
1323 * ftanh FRT,FRB (Rc=0)
1324 * ftanh. FRT,FRB (Rc=1)
1325
1326 Pseudo-code:
1327
1328     FRT <- bfp64_TANH(FRB)
1329
1330 Special Registers Altered:
1331
1332     FPRF FR FI
1333     FX OX UX XX
1334     VXSNAN VXISI VXIMZ
1335     CR1          (if Rc=1)
1336
1337 # [DRAFT] Floating ASINH Single
1338
1339 X-Form
1340
1341 * fasinhs FRT,FRB (Rc=0)
1342 * fasinhs. FRT,FRB (Rc=1)
1343
1344 Pseudo-code:
1345
1346     FRT <- DOUBLE(bfp32_ASINH(SINGLE(FRB)))
1347
1348 Special Registers Altered:
1349
1350     FPRF FR FI
1351     FX OX UX XX
1352     VXSNAN VXISI VXIMZ
1353     CR1          (if Rc=1)
1354
1355 # [DRAFT] Floating ASINH
1356
1357 X-Form
1358
1359 * fasinh FRT,FRB (Rc=0)
1360 * fasinh. FRT,FRB (Rc=1)
1361
1362 Pseudo-code:
1363
1364     FRT <- bfp64_ASINH(FRB)
1365
1366 Special Registers Altered:
1367
1368     FPRF FR FI
1369     FX OX UX XX
1370     VXSNAN VXISI VXIMZ
1371     CR1          (if Rc=1)
1372
1373 # [DRAFT] Floating ACOSH Single
1374
1375 X-Form
1376
1377 * facoshs FRT,FRB (Rc=0)
1378 * facoshs. FRT,FRB (Rc=1)
1379
1380 Pseudo-code:
1381
1382     FRT <- DOUBLE(bfp32_ACOSH(SINGLE(FRB)))
1383
1384 Special Registers Altered:
1385
1386     FPRF FR FI
1387     FX OX UX XX
1388     VXSNAN VXISI VXIMZ
1389     CR1          (if Rc=1)
1390
1391 # [DRAFT] Floating ACOSH
1392
1393 X-Form
1394
1395 * facosh FRT,FRB (Rc=0)
1396 * facosh. FRT,FRB (Rc=1)
1397
1398 Pseudo-code:
1399
1400     FRT <- bfp64_ACOSH(FRB)
1401
1402 Special Registers Altered:
1403
1404     FPRF FR FI
1405     FX OX UX XX
1406     VXSNAN VXISI VXIMZ
1407     CR1          (if Rc=1)
1408
1409 # [DRAFT] Floating ATANH Single
1410
1411 X-Form
1412
1413 * fatanhs FRT,FRB (Rc=0)
1414 * fatanhs. FRT,FRB (Rc=1)
1415
1416 Pseudo-code:
1417
1418     FRT <- DOUBLE(bfp32_ATANH(SINGLE(FRB)))
1419
1420 Special Registers Altered:
1421
1422     FPRF FR FI
1423     FX OX UX XX
1424     VXSNAN VXISI VXIMZ
1425     CR1          (if Rc=1)
1426
1427 # [DRAFT] Floating ATANH
1428
1429 X-Form
1430
1431 * fatanh FRT,FRB (Rc=0)
1432 * fatanh. FRT,FRB (Rc=1)
1433
1434 Pseudo-code:
1435
1436     FRT <- bfp64_ATANH(FRB)
1437
1438 Special Registers Altered:
1439
1440     FPRF FR FI
1441     FX OX UX XX
1442     VXSNAN VXISI VXIMZ
1443     CR1          (if Rc=1)
1444
1445 <!-- fmin*/fmax* need to be replaced with fminmax -->
1446 <!-- commented for now to make encoding space for fmv/cvt -->
1447 <!-- # [DRAFT] Floating MINNUM08 Single -->
1448 <!--  -->
1449 <!-- X-Form -->
1450 <!--  -->
1451 <!-- * fminnum08s FRT,FRA,FRB (Rc=0) -->
1452 <!-- * fminnum08s. FRT,FRA,FRB (Rc=1) -->
1453 <!--  -->
1454 <!-- Pseudo-code: -->
1455 <!--  -->
1456 <!--     FRT <- DOUBLE(bfp32_MINNUM08(SINGLE(FRA), SINGLE(FRB))) -->
1457 <!--  -->
1458 <!-- Special Registers Altered: -->
1459 <!--  -->
1460 <!--     FPRF FR FI -->
1461 <!--     FX OX UX XX -->
1462 <!--     VXSNAN VXISI VXIMZ -->
1463 <!--     CR1          (if Rc=1) -->
1464 <!--  -->
1465 <!-- # [DRAFT] Floating MINNUM08 -->
1466 <!--  -->
1467 <!-- X-Form -->
1468 <!--  -->
1469 <!-- * fminnum08 FRT,FRA,FRB (Rc=0) -->
1470 <!-- * fminnum08. FRT,FRA,FRB (Rc=1) -->
1471 <!--  -->
1472 <!-- Pseudo-code: -->
1473 <!--  -->
1474 <!--     FRT <- bfp64_MINNUM08(FRA, FRB) -->
1475 <!--  -->
1476 <!-- Special Registers Altered: -->
1477 <!--  -->
1478 <!--     FPRF FR FI -->
1479 <!--     FX OX UX XX -->
1480 <!--     VXSNAN VXISI VXIMZ -->
1481 <!--     CR1          (if Rc=1) -->
1482 <!--  -->
1483 <!-- # [DRAFT] Floating MAXNUM08 Single -->
1484 <!--  -->
1485 <!-- X-Form -->
1486 <!--  -->
1487 <!-- * fmaxnum08s FRT,FRA,FRB (Rc=0) -->
1488 <!-- * fmaxnum08s. FRT,FRA,FRB (Rc=1) -->
1489 <!--  -->
1490 <!-- Pseudo-code: -->
1491 <!--  -->
1492 <!--     FRT <- DOUBLE(bfp32_MAXNUM08(SINGLE(FRA), SINGLE(FRB))) -->
1493 <!--  -->
1494 <!-- Special Registers Altered: -->
1495 <!--  -->
1496 <!--     FPRF FR FI -->
1497 <!--     FX OX UX XX -->
1498 <!--     VXSNAN VXISI VXIMZ -->
1499 <!--     CR1          (if Rc=1) -->
1500 <!--  -->
1501 <!-- # [DRAFT] Floating MAXNUM08 -->
1502 <!--  -->
1503 <!-- X-Form -->
1504 <!--  -->
1505 <!-- * fmaxnum08 FRT,FRA,FRB (Rc=0) -->
1506 <!-- * fmaxnum08. FRT,FRA,FRB (Rc=1) -->
1507 <!--  -->
1508 <!-- Pseudo-code: -->
1509 <!--  -->
1510 <!--     FRT <- bfp64_MAXNUM08(FRA, FRB) -->
1511 <!--  -->
1512 <!-- Special Registers Altered: -->
1513 <!--  -->
1514 <!--     FPRF FR FI -->
1515 <!--     FX OX UX XX -->
1516 <!--     VXSNAN VXISI VXIMZ -->
1517 <!--     CR1          (if Rc=1) -->
1518 <!--  -->
1519 <!-- # [DRAFT] Floating MIN19 Single -->
1520 <!--  -->
1521 <!-- X-Form -->
1522 <!--  -->
1523 <!-- * fmin19s FRT,FRA,FRB (Rc=0) -->
1524 <!-- * fmin19s. FRT,FRA,FRB (Rc=1) -->
1525 <!--  -->
1526 <!-- Pseudo-code: -->
1527 <!--  -->
1528 <!--     FRT <- DOUBLE(bfp32_MIN19(SINGLE(FRA), SINGLE(FRB))) -->
1529 <!--  -->
1530 <!-- Special Registers Altered: -->
1531 <!--  -->
1532 <!--     FPRF FR FI -->
1533 <!--     FX OX UX XX -->
1534 <!--     VXSNAN VXISI VXIMZ -->
1535 <!--     CR1          (if Rc=1) -->
1536 <!--  -->
1537 <!-- # [DRAFT] Floating MIN19 -->
1538 <!--  -->
1539 <!-- X-Form -->
1540 <!--  -->
1541 <!-- * fmin19 FRT,FRA,FRB (Rc=0) -->
1542 <!-- * fmin19. FRT,FRA,FRB (Rc=1) -->
1543 <!--  -->
1544 <!-- Pseudo-code: -->
1545 <!--  -->
1546 <!--     FRT <- bfp64_MIN19(FRA, FRB) -->
1547 <!--  -->
1548 <!-- Special Registers Altered: -->
1549 <!--  -->
1550 <!--     FPRF FR FI -->
1551 <!--     FX OX UX XX -->
1552 <!--     VXSNAN VXISI VXIMZ -->
1553 <!--     CR1          (if Rc=1) -->
1554 <!--  -->
1555 <!-- # [DRAFT] Floating MAX19 Single -->
1556 <!--  -->
1557 <!-- X-Form -->
1558 <!--  -->
1559 <!-- * fmax19s FRT,FRA,FRB (Rc=0) -->
1560 <!-- * fmax19s. FRT,FRA,FRB (Rc=1) -->
1561 <!--  -->
1562 <!-- Pseudo-code: -->
1563 <!--  -->
1564 <!--     FRT <- DOUBLE(bfp32_MAX19(SINGLE(FRA), SINGLE(FRB))) -->
1565 <!--  -->
1566 <!-- Special Registers Altered: -->
1567 <!--  -->
1568 <!--     FPRF FR FI -->
1569 <!--     FX OX UX XX -->
1570 <!--     VXSNAN VXISI VXIMZ -->
1571 <!--     CR1          (if Rc=1) -->
1572 <!--  -->
1573 <!-- # [DRAFT] Floating MAX19 -->
1574 <!--  -->
1575 <!-- X-Form -->
1576 <!--  -->
1577 <!-- * fmax19 FRT,FRA,FRB (Rc=0) -->
1578 <!-- * fmax19. FRT,FRA,FRB (Rc=1) -->
1579 <!--  -->
1580 <!-- Pseudo-code: -->
1581 <!--  -->
1582 <!--     FRT <- bfp64_MAX19(FRA, FRB) -->
1583 <!--  -->
1584 <!-- Special Registers Altered: -->
1585 <!--  -->
1586 <!--     FPRF FR FI -->
1587 <!--     FX OX UX XX -->
1588 <!--     VXSNAN VXISI VXIMZ -->
1589 <!--     CR1          (if Rc=1) -->
1590 <!--  -->
1591 <!-- # [DRAFT] Floating MINNUM19 Single -->
1592 <!--  -->
1593 <!-- X-Form -->
1594 <!--  -->
1595 <!-- * fminnum19s FRT,FRA,FRB (Rc=0) -->
1596 <!-- * fminnum19s. FRT,FRA,FRB (Rc=1) -->
1597 <!--  -->
1598 <!-- Pseudo-code: -->
1599 <!--  -->
1600 <!--     FRT <- DOUBLE(bfp32_MINNUM19(SINGLE(FRA), SINGLE(FRB))) -->
1601 <!--  -->
1602 <!-- Special Registers Altered: -->
1603 <!--  -->
1604 <!--     FPRF FR FI -->
1605 <!--     FX OX UX XX -->
1606 <!--     VXSNAN VXISI VXIMZ -->
1607 <!--     CR1          (if Rc=1) -->
1608 <!--  -->
1609 <!-- # [DRAFT] Floating MINNUM19 -->
1610 <!--  -->
1611 <!-- X-Form -->
1612 <!--  -->
1613 <!-- * fminnum19 FRT,FRA,FRB (Rc=0) -->
1614 <!-- * fminnum19. FRT,FRA,FRB (Rc=1) -->
1615 <!--  -->
1616 <!-- Pseudo-code: -->
1617 <!--  -->
1618 <!--     FRT <- bfp64_MINNUM19(FRA, FRB) -->
1619 <!--  -->
1620 <!-- Special Registers Altered: -->
1621 <!--  -->
1622 <!--     FPRF FR FI -->
1623 <!--     FX OX UX XX -->
1624 <!--     VXSNAN VXISI VXIMZ -->
1625 <!--     CR1          (if Rc=1) -->
1626 <!--  -->
1627 <!-- # [DRAFT] Floating MAXNUM19 Single -->
1628 <!--  -->
1629 <!-- X-Form -->
1630 <!--  -->
1631 <!-- * fmaxnum19s FRT,FRA,FRB (Rc=0) -->
1632 <!-- * fmaxnum19s. FRT,FRA,FRB (Rc=1) -->
1633 <!--  -->
1634 <!-- Pseudo-code: -->
1635 <!--  -->
1636 <!--     FRT <- DOUBLE(bfp32_MAXNUM19(SINGLE(FRA), SINGLE(FRB))) -->
1637 <!--  -->
1638 <!-- Special Registers Altered: -->
1639 <!--  -->
1640 <!--     FPRF FR FI -->
1641 <!--     FX OX UX XX -->
1642 <!--     VXSNAN VXISI VXIMZ -->
1643 <!--     CR1          (if Rc=1) -->
1644 <!--  -->
1645 <!-- # [DRAFT] Floating MAXNUM19 -->
1646 <!--  -->
1647 <!-- X-Form -->
1648 <!--  -->
1649 <!-- * fmaxnum19 FRT,FRA,FRB (Rc=0) -->
1650 <!-- * fmaxnum19. FRT,FRA,FRB (Rc=1) -->
1651 <!--  -->
1652 <!-- Pseudo-code: -->
1653 <!--  -->
1654 <!--     FRT <- bfp64_MAXNUM19(FRA, FRB) -->
1655 <!--  -->
1656 <!-- Special Registers Altered: -->
1657 <!--  -->
1658 <!--     FPRF FR FI -->
1659 <!--     FX OX UX XX -->
1660 <!--     VXSNAN VXISI VXIMZ -->
1661 <!--     CR1          (if Rc=1) -->
1662 <!--  -->
1663 <!-- # [DRAFT] Floating MINC Single -->
1664 <!--  -->
1665 <!-- X-Form -->
1666 <!--  -->
1667 <!-- * fmincs FRT,FRA,FRB (Rc=0) -->
1668 <!-- * fmincs. FRT,FRA,FRB (Rc=1) -->
1669 <!--  -->
1670 <!-- Pseudo-code: -->
1671 <!--  -->
1672 <!--     FRT <- DOUBLE(bfp32_MINC(SINGLE(FRA), SINGLE(FRB))) -->
1673 <!--  -->
1674 <!-- Special Registers Altered: -->
1675 <!--  -->
1676 <!--     FPRF FR FI -->
1677 <!--     FX OX UX XX -->
1678 <!--     VXSNAN VXISI VXIMZ -->
1679 <!--     CR1          (if Rc=1) -->
1680 <!--  -->
1681 <!-- # [DRAFT] Floating MINC -->
1682 <!--  -->
1683 <!-- X-Form -->
1684 <!--  -->
1685 <!-- * fminc FRT,FRA,FRB (Rc=0) -->
1686 <!-- * fminc. FRT,FRA,FRB (Rc=1) -->
1687 <!--  -->
1688 <!-- Pseudo-code: -->
1689 <!--  -->
1690 <!--     FRT <- bfp64_MINC(FRA, FRB) -->
1691 <!--  -->
1692 <!-- Special Registers Altered: -->
1693 <!--  -->
1694 <!--     FPRF FR FI -->
1695 <!--     FX OX UX XX -->
1696 <!--     VXSNAN VXISI VXIMZ -->
1697 <!--     CR1          (if Rc=1) -->
1698 <!--  -->
1699 <!-- # [DRAFT] Floating MAXC Single -->
1700 <!--  -->
1701 <!-- X-Form -->
1702 <!--  -->
1703 <!-- * fmaxcs FRT,FRA,FRB (Rc=0) -->
1704 <!-- * fmaxcs. FRT,FRA,FRB (Rc=1) -->
1705 <!--  -->
1706 <!-- Pseudo-code: -->
1707 <!--  -->
1708 <!--     FRT <- DOUBLE(bfp32_MAXC(SINGLE(FRA), SINGLE(FRB))) -->
1709 <!--  -->
1710 <!-- Special Registers Altered: -->
1711 <!--  -->
1712 <!--     FPRF FR FI -->
1713 <!--     FX OX UX XX -->
1714 <!--     VXSNAN VXISI VXIMZ -->
1715 <!--     CR1          (if Rc=1) -->
1716 <!--  -->
1717 <!-- # [DRAFT] Floating MAXC -->
1718 <!--  -->
1719 <!-- X-Form -->
1720 <!--  -->
1721 <!-- * fmaxc FRT,FRA,FRB (Rc=0) -->
1722 <!-- * fmaxc. FRT,FRA,FRB (Rc=1) -->
1723 <!--  -->
1724 <!-- Pseudo-code: -->
1725 <!--  -->
1726 <!--     FRT <- bfp64_MAXC(FRA, FRB) -->
1727 <!--  -->
1728 <!-- Special Registers Altered: -->
1729 <!--  -->
1730 <!--     FPRF FR FI -->
1731 <!--     FX OX UX XX -->
1732 <!--     VXSNAN VXISI VXIMZ -->
1733 <!--     CR1          (if Rc=1) -->
1734 <!--  -->
1735 <!-- # [DRAFT] Floating MINMAGNUM08 Single -->
1736 <!--  -->
1737 <!-- X-Form -->
1738 <!--  -->
1739 <!-- * fminmagnum08s FRT,FRA,FRB (Rc=0) -->
1740 <!-- * fminmagnum08s. FRT,FRA,FRB (Rc=1) -->
1741 <!--  -->
1742 <!-- Pseudo-code: -->
1743 <!--  -->
1744 <!--     FRT <- DOUBLE(bfp32_MINMAGNUM08(SINGLE(FRA), SINGLE(FRB))) -->
1745 <!--  -->
1746 <!-- Special Registers Altered: -->
1747 <!--  -->
1748 <!--     FPRF FR FI -->
1749 <!--     FX OX UX XX -->
1750 <!--     VXSNAN VXISI VXIMZ -->
1751 <!--     CR1          (if Rc=1) -->
1752 <!--  -->
1753 <!-- # [DRAFT] Floating MINMAGNUM08 -->
1754 <!--  -->
1755 <!-- X-Form -->
1756 <!--  -->
1757 <!-- * fminmagnum08 FRT,FRA,FRB (Rc=0) -->
1758 <!-- * fminmagnum08. FRT,FRA,FRB (Rc=1) -->
1759 <!--  -->
1760 <!-- Pseudo-code: -->
1761 <!--  -->
1762 <!--     FRT <- bfp64_MINMAGNUM08(FRA, FRB) -->
1763 <!--  -->
1764 <!-- Special Registers Altered: -->
1765 <!--  -->
1766 <!--     FPRF FR FI -->
1767 <!--     FX OX UX XX -->
1768 <!--     VXSNAN VXISI VXIMZ -->
1769 <!--     CR1          (if Rc=1) -->
1770 <!--  -->
1771 <!-- # [DRAFT] Floating MAXMAGNUM08 Single -->
1772 <!--  -->
1773 <!-- X-Form -->
1774 <!--  -->
1775 <!-- * fmaxmagnum08s FRT,FRA,FRB (Rc=0) -->
1776 <!-- * fmaxmagnum08s. FRT,FRA,FRB (Rc=1) -->
1777 <!--  -->
1778 <!-- Pseudo-code: -->
1779 <!--  -->
1780 <!--     FRT <- DOUBLE(bfp32_MAXMAGNUM08(SINGLE(FRA), SINGLE(FRB))) -->
1781 <!--  -->
1782 <!-- Special Registers Altered: -->
1783 <!--  -->
1784 <!--     FPRF FR FI -->
1785 <!--     FX OX UX XX -->
1786 <!--     VXSNAN VXISI VXIMZ -->
1787 <!--     CR1          (if Rc=1) -->
1788 <!--  -->
1789 <!-- # [DRAFT] Floating MAXMAGNUM08 -->
1790 <!--  -->
1791 <!-- X-Form -->
1792 <!--  -->
1793 <!-- * fmaxmagnum08 FRT,FRA,FRB (Rc=0) -->
1794 <!-- * fmaxmagnum08. FRT,FRA,FRB (Rc=1) -->
1795 <!--  -->
1796 <!-- Pseudo-code: -->
1797 <!--  -->
1798 <!--     FRT <- bfp64_MAXMAGNUM08(FRA, FRB) -->
1799 <!--  -->
1800 <!-- Special Registers Altered: -->
1801 <!--  -->
1802 <!--     FPRF FR FI -->
1803 <!--     FX OX UX XX -->
1804 <!--     VXSNAN VXISI VXIMZ -->
1805 <!--     CR1          (if Rc=1) -->
1806 <!--  -->
1807 <!-- # [DRAFT] Floating MINMAG19 Single -->
1808 <!--  -->
1809 <!-- X-Form -->
1810 <!--  -->
1811 <!-- * fminmag19s FRT,FRA,FRB (Rc=0) -->
1812 <!-- * fminmag19s. FRT,FRA,FRB (Rc=1) -->
1813 <!--  -->
1814 <!-- Pseudo-code: -->
1815 <!--  -->
1816 <!--     FRT <- DOUBLE(bfp32_MINMAG19(SINGLE(FRA), SINGLE(FRB))) -->
1817 <!--  -->
1818 <!-- Special Registers Altered: -->
1819 <!--  -->
1820 <!--     FPRF FR FI -->
1821 <!--     FX OX UX XX -->
1822 <!--     VXSNAN VXISI VXIMZ -->
1823 <!--     CR1          (if Rc=1) -->
1824 <!--  -->
1825 <!-- # [DRAFT] Floating MINMAG19 -->
1826 <!--  -->
1827 <!-- X-Form -->
1828 <!--  -->
1829 <!-- * fminmag19 FRT,FRA,FRB (Rc=0) -->
1830 <!-- * fminmag19. FRT,FRA,FRB (Rc=1) -->
1831 <!--  -->
1832 <!-- Pseudo-code: -->
1833 <!--  -->
1834 <!--     FRT <- bfp64_MINMAG19(FRA, FRB) -->
1835 <!--  -->
1836 <!-- Special Registers Altered: -->
1837 <!--  -->
1838 <!--     FPRF FR FI -->
1839 <!--     FX OX UX XX -->
1840 <!--     VXSNAN VXISI VXIMZ -->
1841 <!--     CR1          (if Rc=1) -->
1842 <!--  -->
1843 <!-- # [DRAFT] Floating MAXMAG19 Single -->
1844 <!--  -->
1845 <!-- X-Form -->
1846 <!--  -->
1847 <!-- * fmaxmag19s FRT,FRA,FRB (Rc=0) -->
1848 <!-- * fmaxmag19s. FRT,FRA,FRB (Rc=1) -->
1849 <!--  -->
1850 <!-- Pseudo-code: -->
1851 <!--  -->
1852 <!--     FRT <- DOUBLE(bfp32_MAXMAG19(SINGLE(FRA), SINGLE(FRB))) -->
1853 <!--  -->
1854 <!-- Special Registers Altered: -->
1855 <!--  -->
1856 <!--     FPRF FR FI -->
1857 <!--     FX OX UX XX -->
1858 <!--     VXSNAN VXISI VXIMZ -->
1859 <!--     CR1          (if Rc=1) -->
1860 <!--  -->
1861 <!-- # [DRAFT] Floating MAXMAG19 -->
1862 <!--  -->
1863 <!-- X-Form -->
1864 <!--  -->
1865 <!-- * fmaxmag19 FRT,FRA,FRB (Rc=0) -->
1866 <!-- * fmaxmag19. FRT,FRA,FRB (Rc=1) -->
1867 <!--  -->
1868 <!-- Pseudo-code: -->
1869 <!--  -->
1870 <!--     FRT <- bfp64_MAXMAG19(FRA, FRB) -->
1871 <!--  -->
1872 <!-- Special Registers Altered: -->
1873 <!--  -->
1874 <!--     FPRF FR FI -->
1875 <!--     FX OX UX XX -->
1876 <!--     VXSNAN VXISI VXIMZ -->
1877 <!--     CR1          (if Rc=1) -->
1878 <!--  -->
1879 <!-- # [DRAFT] Floating MINMAGNUM19 Single -->
1880 <!--  -->
1881 <!-- X-Form -->
1882 <!--  -->
1883 <!-- * fminmagnum19s FRT,FRA,FRB (Rc=0) -->
1884 <!-- * fminmagnum19s. FRT,FRA,FRB (Rc=1) -->
1885 <!--  -->
1886 <!-- Pseudo-code: -->
1887 <!--  -->
1888 <!--     FRT <- DOUBLE(bfp32_MINMAGNUM19(SINGLE(FRA), SINGLE(FRB))) -->
1889 <!--  -->
1890 <!-- Special Registers Altered: -->
1891 <!--  -->
1892 <!--     FPRF FR FI -->
1893 <!--     FX OX UX XX -->
1894 <!--     VXSNAN VXISI VXIMZ -->
1895 <!--     CR1          (if Rc=1) -->
1896 <!--  -->
1897 <!-- # [DRAFT] Floating MINMAGNUM19 -->
1898 <!--  -->
1899 <!-- X-Form -->
1900 <!--  -->
1901 <!-- * fminmagnum19 FRT,FRA,FRB (Rc=0) -->
1902 <!-- * fminmagnum19. FRT,FRA,FRB (Rc=1) -->
1903 <!--  -->
1904 <!-- Pseudo-code: -->
1905 <!--  -->
1906 <!--     FRT <- bfp64_MINMAGNUM19(FRA, FRB) -->
1907 <!--  -->
1908 <!-- Special Registers Altered: -->
1909 <!--  -->
1910 <!--     FPRF FR FI -->
1911 <!--     FX OX UX XX -->
1912 <!--     VXSNAN VXISI VXIMZ -->
1913 <!--     CR1          (if Rc=1) -->
1914 <!--  -->
1915 <!-- # [DRAFT] Floating MAXMAGNUM19 Single -->
1916 <!--  -->
1917 <!-- X-Form -->
1918 <!--  -->
1919 <!-- * fmaxmagnum19s FRT,FRA,FRB (Rc=0) -->
1920 <!-- * fmaxmagnum19s. FRT,FRA,FRB (Rc=1) -->
1921 <!--  -->
1922 <!-- Pseudo-code: -->
1923 <!--  -->
1924 <!--     FRT <- DOUBLE(bfp32_MAXMAGNUM19(SINGLE(FRA), SINGLE(FRB))) -->
1925 <!--  -->
1926 <!-- Special Registers Altered: -->
1927 <!--  -->
1928 <!--     FPRF FR FI -->
1929 <!--     FX OX UX XX -->
1930 <!--     VXSNAN VXISI VXIMZ -->
1931 <!--     CR1          (if Rc=1) -->
1932 <!--  -->
1933 <!-- # [DRAFT] Floating MAXMAGNUM19 -->
1934 <!--  -->
1935 <!-- X-Form -->
1936 <!--  -->
1937 <!-- * fmaxmagnum19 FRT,FRA,FRB (Rc=0) -->
1938 <!-- * fmaxmagnum19. FRT,FRA,FRB (Rc=1) -->
1939 <!--  -->
1940 <!-- Pseudo-code: -->
1941 <!--  -->
1942 <!--     FRT <- bfp64_MAXMAGNUM19(FRA, FRB) -->
1943 <!--  -->
1944 <!-- Special Registers Altered: -->
1945 <!--  -->
1946 <!--     FPRF FR FI -->
1947 <!--     FX OX UX XX -->
1948 <!--     VXSNAN VXISI VXIMZ -->
1949 <!--     CR1          (if Rc=1) -->
1950 <!--  -->
1951 <!-- # [DRAFT] Floating MINMAGC Single -->
1952 <!--  -->
1953 <!-- X-Form -->
1954 <!--  -->
1955 <!-- * fminmagcs FRT,FRA,FRB (Rc=0) -->
1956 <!-- * fminmagcs. FRT,FRA,FRB (Rc=1) -->
1957 <!--  -->
1958 <!-- Pseudo-code: -->
1959 <!--  -->
1960 <!--     FRT <- DOUBLE(bfp32_MINMAGC(SINGLE(FRA), SINGLE(FRB))) -->
1961 <!--  -->
1962 <!-- Special Registers Altered: -->
1963 <!--  -->
1964 <!--     FPRF FR FI -->
1965 <!--     FX OX UX XX -->
1966 <!--     VXSNAN VXISI VXIMZ -->
1967 <!--     CR1          (if Rc=1) -->
1968 <!--  -->
1969 <!-- # [DRAFT] Floating MINMAGC -->
1970 <!--  -->
1971 <!-- X-Form -->
1972 <!--  -->
1973 <!-- * fminmagc FRT,FRA,FRB (Rc=0) -->
1974 <!-- * fminmagc. FRT,FRA,FRB (Rc=1) -->
1975 <!--  -->
1976 <!-- Pseudo-code: -->
1977 <!--  -->
1978 <!--     FRT <- bfp64_MINMAGC(FRA, FRB) -->
1979 <!--  -->
1980 <!-- Special Registers Altered: -->
1981 <!--  -->
1982 <!--     FPRF FR FI -->
1983 <!--     FX OX UX XX -->
1984 <!--     VXSNAN VXISI VXIMZ -->
1985 <!--     CR1          (if Rc=1) -->
1986 <!--  -->
1987 <!-- # [DRAFT] Floating MAXMAGC Single -->
1988 <!--  -->
1989 <!-- X-Form -->
1990 <!--  -->
1991 <!-- * fmaxmagcs FRT,FRA,FRB (Rc=0) -->
1992 <!-- * fmaxmagcs. FRT,FRA,FRB (Rc=1) -->
1993 <!--  -->
1994 <!-- Pseudo-code: -->
1995 <!--  -->
1996 <!--     FRT <- DOUBLE(bfp32_MAXMAGC(SINGLE(FRA), SINGLE(FRB))) -->
1997 <!--  -->
1998 <!-- Special Registers Altered: -->
1999 <!--  -->
2000 <!--     FPRF FR FI -->
2001 <!--     FX OX UX XX -->
2002 <!--     VXSNAN VXISI VXIMZ -->
2003 <!--     CR1          (if Rc=1) -->
2004 <!--  -->
2005 <!-- # [DRAFT] Floating MAXMAGC -->
2006 <!--  -->
2007 <!-- X-Form -->
2008 <!--  -->
2009 <!-- * fmaxmagc FRT,FRA,FRB (Rc=0) -->
2010 <!-- * fmaxmagc. FRT,FRA,FRB (Rc=1) -->
2011 <!--  -->
2012 <!-- Pseudo-code: -->
2013 <!--  -->
2014 <!--     FRT <- bfp64_MAXMAGC(FRA, FRB) -->
2015 <!--  -->
2016 <!-- Special Registers Altered: -->
2017 <!--  -->
2018 <!--     FPRF FR FI -->
2019 <!--     FX OX UX XX -->
2020 <!--     VXSNAN VXISI VXIMZ -->
2021 <!--     CR1          (if Rc=1) -->
2022
2023 # [DRAFT] Floating MOD Single
2024
2025 X-Form
2026
2027 * fmods FRT,FRA,FRB (Rc=0)
2028 * fmods. FRT,FRA,FRB (Rc=1)
2029
2030 Pseudo-code:
2031
2032     FRT <- DOUBLE(bfp32_MOD(SINGLE(FRA), SINGLE(FRB)))
2033
2034 Special Registers Altered:
2035
2036     FPRF FR FI
2037     FX OX UX XX
2038     VXSNAN VXISI VXIMZ
2039     CR1          (if Rc=1)
2040
2041 # [DRAFT] Floating MOD
2042
2043 X-Form
2044
2045 * fmod FRT,FRA,FRB (Rc=0)
2046 * fmod. FRT,FRA,FRB (Rc=1)
2047
2048 Pseudo-code:
2049
2050     FRT <- bfp64_MOD(FRA, FRB)
2051
2052 Special Registers Altered:
2053
2054     FPRF FR FI
2055     FX OX UX XX
2056     VXSNAN VXISI VXIMZ
2057     CR1          (if Rc=1)
2058
2059 # [DRAFT] Floating REMAINDER Single
2060
2061 X-Form
2062
2063 * fremainders FRT,FRA,FRB (Rc=0)
2064 * fremainders. FRT,FRA,FRB (Rc=1)
2065
2066 Pseudo-code:
2067
2068     FRT <- DOUBLE(bfp32_REMAINDER(SINGLE(FRA), SINGLE(FRB)))
2069
2070 Special Registers Altered:
2071
2072     FPRF FR FI
2073     FX OX UX XX
2074     VXSNAN VXISI VXIMZ
2075     CR1          (if Rc=1)
2076
2077 # [DRAFT] Floating REMAINDER
2078
2079 X-Form
2080
2081 * fremainder FRT,FRA,FRB (Rc=0)
2082 * fremainder. FRT,FRA,FRB (Rc=1)
2083
2084 Pseudo-code:
2085
2086     FRT <- bfp64_REMAINDER(FRA, FRB)
2087
2088 Special Registers Altered:
2089
2090     FPRF FR FI
2091     FX OX UX XX
2092     VXSNAN VXISI VXIMZ
2093     CR1          (if Rc=1)
2094