openpower/isa/pifixedload.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update
  12
  13 D-Form
  14
  15 * lbzup RT,D(RA)
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + EXTS(D)
  22
  23 Description:
  24
  25     Let the effective address (EA) be register RA. The
  26     byte in storage addressed by EA is loaded into RT[56:63].
  27     RT[0:55] are set to 0.
  28
  29     The sum (RA) + D is placed into register RA.
  30
  31     If RA=0 or RA=RT, the instruction form is invalid.
  32
  33 Special Registers Altered:
  34
  35     None
  36
  37 # Load Byte and Zero with Post-Update Indexed
  38
  39 X-Form
  40
  41 * lbzupx RT,RA,RB
  42
  43 Pseudo-code:
  44
  45     EA <- (RA)
  46     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  47     RA <- (RA) + (RB)
  48
  49 Special Registers Altered:
  50
  51     None
  52
  53 # Load Halfword and Zero with Post-Update
  54
  55 D-Form
  56
  57 * lhzup RT,D(RA)
  58
  59 Pseudo-code:
  60
  61     EA <- (RA)
  62     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  63     RA <- (RA) + EXTS(D)
  64
  65 Special Registers Altered:
  66
  67     None
  68
  69 # Load Halfword and Zero with Post-Update Indexed
  70
  71 X-Form
  72
  73 * lhzupx RT,RA,RB
  74
  75 Pseudo-code:
  76
  77     EA <- (RA)
  78     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  79     RA <- (RA) + (RB)
  80
  81 Special Registers Altered:
  82
  83     None
  84
  85 # Load Halfword Algebraic with Post-Update
  86
  87 D-Form
  88
  89 * lhaup RT,D(RA)
  90
  91 Pseudo-code:
  92
  93     EA <- (RA)
  94     RT <- EXTS(MEM(EA, 2))
  95     RA <- (RA) + EXTS(D)
  96
  97 Special Registers Altered:
  98
  99     None
 100
 101 # Load Halfword Algebraic with Post-Update Indexed
 102
 103 X-Form
 104
 105 * lhaupx RT,RA,RB
 106
 107 Pseudo-code:
 108
 109     EA <- (RA)
 110     RT <- EXTS(MEM(EA, 2))
 111     RA <- (RA) + (RB)
 112
 113 Special Registers Altered:
 114
 115     None
 116
 117 # Load Word and Zero with Post-Update
 118
 119 D-Form
 120
 121 * lwzup RT,D(RA)
 122
 123 Pseudo-code:
 124
 125     EA <- (RA)
 126     RT <- [0]*32 || MEM(EA, 4)
 127     RA <- (RA) + EXTS(D)
 128
 129 Special Registers Altered:
 130
 131     None
 132
 133 # Load Word and Zero with Post-Update Indexed
 134
 135 X-Form
 136
 137 * lwzupx RT,RA,RB
 138
 139 Pseudo-code:
 140
 141     EA <- (RA)
 142     RT <- [0] * 32 || MEM(EA, 4)
 143     RA <- (RA) + (RB)
 144
 145 Special Registers Altered:
 146
 147     None
 148
 149 # Load Word Algebraic with Post-Update Indexed
 150
 151 X-Form
 152
 153 * lwaupx RT,RA,RB
 154
 155 Pseudo-code:
 156
 157     EA <- (RA)
 158     RT <- EXTS(MEM(EA, 4))
 159     RA <- (RA) + (RB)
 160
 161 Special Registers Altered:
 162
 163     None
 164
 165 # Load Doubleword with Post-Update Indexed
 166
 167 DS-Form
 168
 169 * ldup RT,DS(RA)
 170
 171 Pseudo-code:
 172
 173     EA <- (RA)
 174     RT <- MEM(EA, 8)
 175     RA <- (RA) + EXTS(DS || 0b00)
 176
 177 Special Registers Altered:
 178
 179     None
 180
 181 # Load Doubleword with Post-Update Indexed
 182
 183 X-Form
 184
 185 * ldupx RT,RA,RB
 186
 187 Pseudo-code:
 188
 189     EA <- (RA)
 190     RT <- MEM(EA, 8)
 191     RA <- (RA) + (RB)
 192
 193 Special Registers Altered:
 194
 195     None
 196