1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
3 <!-- This defines instructions that load from RAM to a register -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 <!-- Note that these pages also define equivalent store instructions, -->
7 <!-- these are described in pifixedstore.mdwn -->
11 # Load Byte and Zero with Post-Update
20 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
25 Let the effective address (EA) be register RA. The
26 byte in storage addressed by EA is loaded into RT[56:63].
27 RT[0:55] are set to 0.
29 The sum (RA) + D is placed into register RA.
31 If RA=0 or RA=RT, the instruction form is invalid.
33 Special Registers Altered:
37 # Load Byte and Zero with Post-Update Indexed
46 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
51 Let the effective address (EA) be register RA.
52 The byte in storage addressed by EA is loaded into
53 RT[56:63]. RT[0:55] are set to 0.
55 The sum (RA) + (RB) is placed into register RA.
57 If RA=0 or RA=RT, the instruction form is invalid.
59 Special Registers Altered:
63 # Load Halfword and Zero with Post-Update
72 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
75 Special Registers Altered:
79 # Load Halfword and Zero with Post-Update Indexed
88 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
91 Special Registers Altered:
95 # Load Halfword Algebraic with Post-Update
104 RT <- EXTS(MEM(EA, 2))
107 Special Registers Altered:
111 # Load Halfword Algebraic with Post-Update Indexed
120 RT <- EXTS(MEM(EA, 2))
123 Special Registers Altered:
127 # Load Word and Zero with Post-Update
136 RT <- [0]*32 || MEM(EA, 4)
139 Special Registers Altered:
143 # Load Word and Zero with Post-Update Indexed
152 RT <- [0] * 32 || MEM(EA, 4)
155 Special Registers Altered:
159 # Load Word Algebraic with Post-Update Indexed
168 RT <- EXTS(MEM(EA, 4))
171 Special Registers Altered:
175 # Load Doubleword with Post-Update Indexed
185 RA <- (RA) + EXTS(DS || 0b00)
187 Special Registers Altered:
191 # Load Doubleword with Post-Update Indexed
203 Special Registers Altered: