1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
3 <!-- This defines instructions that load from RAM to a register -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 <!-- Note that these pages also define equivalent store instructions, -->
7 <!-- these are described in pifixedstore.mdwn -->
11 # Load Byte and Zero with Post-Update
20 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
23 Special Registers Altered:
27 # Load Byte and Zero with Post-Update Indexed
36 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
39 Special Registers Altered:
43 # Load Halfword and Zero with Post-Update
52 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
55 Special Registers Altered:
59 # Load Halfword and Zero with Post-Update Indexed
68 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
71 Special Registers Altered:
75 # Load Halfword Algebraic with Post-Update
84 RT <- EXTS(MEM(EA, 2))
87 Special Registers Altered:
91 # Load Halfword Algebraic with Post-Update Indexed
100 RT <- EXTS(MEM(EA, 2))
103 Special Registers Altered:
107 # Load Word and Zero with Post-Update
116 RT <- [0]*32 || MEM(EA, 4)
119 Special Registers Altered:
123 # Load Word and Zero with Post-Update Indexed
132 RT <- [0] * 32 || MEM(EA, 4)
135 Special Registers Altered:
139 # Load Word Algebraic with Post-Update Indexed
148 RT <- EXTS(MEM(EA, 4))
151 Special Registers Altered:
155 # Load Doubleword with Post-Update Indexed
165 RA <- (RA) + EXTS(DS || 0b00)
167 Special Registers Altered:
171 # Load Doubleword with Post-Update Indexed
183 Special Registers Altered: