1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
3 <!-- This defines instructions that load from RAM to a register -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 <!-- Note that these pages also define equivalent store instructions, -->
7 <!-- these are described in pifixedstore.mdwn -->
11 # Load Byte and Zero with Post-Update
20 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
25 Let the effective address (EA) be register RA.
26 The byte in storage addressed by EA is loaded into RT[56:63].
27 RT[0:55] are set to 0.
29 The sum (RA) + D is placed into register RA.
31 If RA=0 or RA=RT, the instruction form is invalid.
33 Special Registers Altered:
37 # Load Byte and Zero with Post-Update Indexed
46 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
51 Let the effective address (EA) be register RA.
52 The byte in storage addressed by EA is loaded into RT[56:63].
53 RT[0:55] are set to 0.
55 The sum (RA) + (RB) is placed into register RA.
57 If RA=0 or RA=RT, the instruction form is invalid.
59 Special Registers Altered:
63 # Load Halfword and Zero with Post-Update
72 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
77 Let the effective address (EA) be register RA.
78 The halfword in storage addressed by EA is loaded into RT[48:63].
79 RT[0:47] are set to 0.
81 The sum (RA) + D is placed into register RA.
83 If RA=0 or RA=RT, the instruction form is invalid.
85 Special Registers Altered:
89 # Load Halfword and Zero with Post-Update Indexed
98 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
103 Let the effective address (EA) be register RA.
104 The halfword in storage addressed by EA is loaded into RT[48:63].
105 RT[0:47] are set to 0.
107 The sum (RA) + (RB) is placed into register RA.
109 If RA=0 or RA=RT, the instruction form is invalid.
111 Special Registers Altered:
115 # Load Halfword Algebraic with Post-Update
124 RT <- EXTS(MEM(EA, 2))
129 Let the effective address (EA) be the register RA.
130 The halfword in storage addressed by EA is loaded into RT[48:63].
131 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
133 Special Registers Altered:
137 # Load Halfword Algebraic with Post-Update Indexed
146 RT <- EXTS(MEM(EA, 2))
149 Special Registers Altered:
153 # Load Word and Zero with Post-Update
162 RT <- [0]*32 || MEM(EA, 4)
165 Special Registers Altered:
169 # Load Word and Zero with Post-Update Indexed
178 RT <- [0] * 32 || MEM(EA, 4)
181 Special Registers Altered:
185 # Load Word Algebraic with Post-Update Indexed
194 RT <- EXTS(MEM(EA, 4))
197 Special Registers Altered:
201 # Load Doubleword with Post-Update Indexed
211 RA <- (RA) + EXTS(DS || 0b00)
213 Special Registers Altered:
217 # Load Doubleword with Post-Update Indexed
229 Special Registers Altered: