openpower/isa/pifixedload.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update
  12
  13 D-Form
  14
  15 * lbzup RT,D(RA)
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + EXTS(D)
  22
  23 Description:
  24
  25     Let the effective address (EA) be register RA. The
  26     byte in storage addressed by EA is loaded into RT[56:63].
  27     RT[0:55] are set to 0.
  28
  29     The sum (RA) + D is placed into register RA.
  30
  31     If RA=0 or RA=RT, the instruction form is invalid.
  32
  33 Special Registers Altered:
  34
  35     None
  36
  37 # Load Byte and Zero with Post-Update Indexed
  38
  39 X-Form
  40
  41 * lbzupx RT,RA,RB
  42
  43 Pseudo-code:
  44
  45     EA <- (RA)
  46     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  47     RA <- (RA) + (RB)
  48
  49 Description:
  50
  51     Let the effective address (EA) be register RA.
  52     The byte in storage addressed by EA is loaded into
  53     RT[56:63]. RT[0:55] are set to 0.
  54
  55     The sum (RA) + (RB) is placed into register RA.
  56
  57     If RA=0 or RA=RT, the instruction form is invalid.
  58
  59 Special Registers Altered:
  60
  61     None
  62
  63 # Load Halfword and Zero with Post-Update
  64
  65 D-Form
  66
  67 * lhzup RT,D(RA)
  68
  69 Pseudo-code:
  70
  71     EA <- (RA)
  72     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  73     RA <- (RA) + EXTS(D)
  74
  75 Description:
  76
  77     Let the effective address (EA) be register RA. The
  78     halfword in storage addressed by EA is loaded into
  79     RT[48:63]. RT[0:47] are set to 0.
  80
  81     The sum (RA) + D is placed into register RA.
  82
  83     If RA=0 or RA=RT, the instruction form is invalid.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Halfword and Zero with Post-Update Indexed
  90
  91 X-Form
  92
  93 * lhzupx RT,RA,RB
  94
  95 Pseudo-code:
  96
  97     EA <- (RA)
  98     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  99     RA <- (RA) + (RB)
 100
 101 Description:
 102
 103     Let the effective address (EA) be register RA.
 104     The halfword in storage addressed by EA is loaded into
 105     RT[48:63]. RT[0:47] are set to 0.
 106
 107     The sum (RA) + (RB) is placed into register RA.
 108
 109     If RA=0 or RA=RT, the instruction form is invalid.
 110
 111 Special Registers Altered:
 112
 113     None
 114
 115 # Load Halfword Algebraic with Post-Update
 116
 117 D-Form
 118
 119 * lhaup RT,D(RA)
 120
 121 Pseudo-code:
 122
 123     EA <- (RA)
 124     RT <- EXTS(MEM(EA, 2))
 125     RA <- (RA) + EXTS(D)
 126
 127 Special Registers Altered:
 128
 129     None
 130
 131 # Load Halfword Algebraic with Post-Update Indexed
 132
 133 X-Form
 134
 135 * lhaupx RT,RA,RB
 136
 137 Pseudo-code:
 138
 139     EA <- (RA)
 140     RT <- EXTS(MEM(EA, 2))
 141     RA <- (RA) + (RB)
 142
 143 Special Registers Altered:
 144
 145     None
 146
 147 # Load Word and Zero with Post-Update
 148
 149 D-Form
 150
 151 * lwzup RT,D(RA)
 152
 153 Pseudo-code:
 154
 155     EA <- (RA)
 156     RT <- [0]*32 || MEM(EA, 4)
 157     RA <- (RA) + EXTS(D)
 158
 159 Special Registers Altered:
 160
 161     None
 162
 163 # Load Word and Zero with Post-Update Indexed
 164
 165 X-Form
 166
 167 * lwzupx RT,RA,RB
 168
 169 Pseudo-code:
 170
 171     EA <- (RA)
 172     RT <- [0] * 32 || MEM(EA, 4)
 173     RA <- (RA) + (RB)
 174
 175 Special Registers Altered:
 176
 177     None
 178
 179 # Load Word Algebraic with Post-Update Indexed
 180
 181 X-Form
 182
 183 * lwaupx RT,RA,RB
 184
 185 Pseudo-code:
 186
 187     EA <- (RA)
 188     RT <- EXTS(MEM(EA, 4))
 189     RA <- (RA) + (RB)
 190
 191 Special Registers Altered:
 192
 193     None
 194
 195 # Load Doubleword with Post-Update Indexed
 196
 197 DS-Form
 198
 199 * ldup RT,DS(RA)
 200
 201 Pseudo-code:
 202
 203     EA <- (RA)
 204     RT <- MEM(EA, 8)
 205     RA <- (RA) + EXTS(DS || 0b00)
 206
 207 Special Registers Altered:
 208
 209     None
 210
 211 # Load Doubleword with Post-Update Indexed
 212
 213 X-Form
 214
 215 * ldupx RT,RA,RB
 216
 217 Pseudo-code:
 218
 219     EA <- (RA)
 220     RT <- MEM(EA, 8)
 221     RA <- (RA) + (RB)
 222
 223 Special Registers Altered:
 224
 225     None
 226