1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
3 <!-- This defines instructions that load from RAM to a register -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 <!-- Note that these pages also define equivalent store instructions, -->
7 <!-- these are described in pifixedstore.mdwn -->
11 # Load Byte and Zero with Post-Update
20 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
25 Let the effective address (EA) be register RA. The
26 byte in storage addressed by EA is loaded into RT[56:63].
27 RT[0:55] are set to 0.
29 The sum (RA) + D is placed into register RA.
31 If RA=0 or RA=RT, the instruction form is invalid.
33 Special Registers Altered:
37 # Load Byte and Zero with Post-Update Indexed
46 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
49 Special Registers Altered:
53 # Load Halfword and Zero with Post-Update
62 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
65 Special Registers Altered:
69 # Load Halfword and Zero with Post-Update Indexed
78 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
81 Special Registers Altered:
85 # Load Halfword Algebraic with Post-Update
94 RT <- EXTS(MEM(EA, 2))
97 Special Registers Altered:
101 # Load Halfword Algebraic with Post-Update Indexed
110 RT <- EXTS(MEM(EA, 2))
113 Special Registers Altered:
117 # Load Word and Zero with Post-Update
126 RT <- [0]*32 || MEM(EA, 4)
129 Special Registers Altered:
133 # Load Word and Zero with Post-Update Indexed
142 RT <- [0] * 32 || MEM(EA, 4)
145 Special Registers Altered:
149 # Load Word Algebraic with Post-Update Indexed
158 RT <- EXTS(MEM(EA, 4))
161 Special Registers Altered:
165 # Load Doubleword with Post-Update Indexed
175 RA <- (RA) + EXTS(DS || 0b00)
177 Special Registers Altered:
181 # Load Doubleword with Post-Update Indexed
193 Special Registers Altered: