openpower/isa/pifixedload.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update
  12
  13 D-Form
  14
  15 * lbzup RT,D(RA)
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + EXTS(D)
  22
  23 Description:
  24
  25     Let the effective address (EA) be register RA.
  26     The byte in storage addressed by EA is loaded into RT[56:63].
  27     RT[0:55] are set to 0.
  28
  29     The sum (RA) + D is placed into register RA.
  30
  31     If RA=0 or RA=RT, the instruction form is invalid.
  32
  33 Special Registers Altered:
  34
  35     None
  36
  37 # Load Byte and Zero with Post-Update Indexed
  38
  39 X-Form
  40
  41 * lbzupx RT,RA,RB
  42
  43 Pseudo-code:
  44
  45     EA <- (RA)
  46     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  47     RA <- (RA) + (RB)
  48
  49 Description:
  50
  51     Let the effective address (EA) be register RA.
  52     The byte in storage addressed by EA is loaded into RT[56:63].
  53     RT[0:55] are set to 0.
  54
  55     The sum (RA) + (RB) is placed into register RA.
  56
  57     If RA=0 or RA=RT, the instruction form is invalid.
  58
  59 Special Registers Altered:
  60
  61     None
  62
  63 # Load Halfword and Zero with Post-Update
  64
  65 D-Form
  66
  67 * lhzup RT,D(RA)
  68
  69 Pseudo-code:
  70
  71     EA <- (RA)
  72     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  73     RA <- (RA) + EXTS(D)
  74
  75 Description:
  76
  77     Let the effective address (EA) be register RA.
  78     The halfword in storage addressed by EA is loaded into RT[48:63].
  79     RT[0:47] are set to 0.
  80
  81     The sum (RA) + D is placed into register RA.
  82
  83     If RA=0 or RA=RT, the instruction form is invalid.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Halfword and Zero with Post-Update Indexed
  90
  91 X-Form
  92
  93 * lhzupx RT,RA,RB
  94
  95 Pseudo-code:
  96
  97     EA <- (RA)
  98     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  99     RA <- (RA) + (RB)
 100
 101 Description:
 102
 103     Let the effective address (EA) be register RA.
 104     The halfword in storage addressed by EA is loaded into RT[48:63].
 105     RT[0:47] are set to 0.
 106
 107     The sum (RA) + (RB) is placed into register RA.
 108
 109     If RA=0 or RA=RT, the instruction form is invalid.
 110
 111 Special Registers Altered:
 112
 113     None
 114
 115 # Load Halfword Algebraic with Post-Update
 116
 117 D-Form
 118
 119 * lhaup RT,D(RA)
 120
 121 Pseudo-code:
 122
 123     EA <- (RA)
 124     RT <- EXTS(MEM(EA, 2))
 125     RA <- (RA) + EXTS(D)
 126
 127 Description:
 128
 129     Let the effective address (EA) be the register RA.
 130     The halfword in storage addressed by EA is loaded into RT[48:63].
 131     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 132
 133     The sum (RA) + D is placed into register RA.
 134
 135     If RA=0 or RA=RT, the instruction form is invalid.
 136
 137 Special Registers Altered:
 138
 139     None
 140
 141 # Load Halfword Algebraic with Post-Update Indexed
 142
 143 X-Form
 144
 145 * lhaupx RT,RA,RB
 146
 147 Pseudo-code:
 148
 149     EA <- (RA)
 150     RT <- EXTS(MEM(EA, 2))
 151     RA <- (RA) + (RB)
 152
 153 Description:
 154
 155     Let the effective address (EA) be the register RA.
 156     The halfword in storage addressed by EA is loaded into RT[48:63].
 157     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 158
 159     The sum (RA) + (RB) is placed into register RA.
 160
 161 Special Registers Altered:
 162
 163     None
 164
 165 # Load Word and Zero with Post-Update
 166
 167 D-Form
 168
 169 * lwzup RT,D(RA)
 170
 171 Pseudo-code:
 172
 173     EA <- (RA)
 174     RT <- [0]*32 || MEM(EA, 4)
 175     RA <- (RA) + EXTS(D)
 176
 177 Special Registers Altered:
 178
 179     None
 180
 181 # Load Word and Zero with Post-Update Indexed
 182
 183 X-Form
 184
 185 * lwzupx RT,RA,RB
 186
 187 Pseudo-code:
 188
 189     EA <- (RA)
 190     RT <- [0] * 32 || MEM(EA, 4)
 191     RA <- (RA) + (RB)
 192
 193 Special Registers Altered:
 194
 195     None
 196
 197 # Load Word Algebraic with Post-Update Indexed
 198
 199 X-Form
 200
 201 * lwaupx RT,RA,RB
 202
 203 Pseudo-code:
 204
 205     EA <- (RA)
 206     RT <- EXTS(MEM(EA, 4))
 207     RA <- (RA) + (RB)
 208
 209 Special Registers Altered:
 210
 211     None
 212
 213 # Load Doubleword with Post-Update Indexed
 214
 215 DS-Form
 216
 217 * ldup RT,DS(RA)
 218
 219 Pseudo-code:
 220
 221     EA <- (RA)
 222     RT <- MEM(EA, 8)
 223     RA <- (RA) + EXTS(DS || 0b00)
 224
 225 Special Registers Altered:
 226
 227     None
 228
 229 # Load Doubleword with Post-Update Indexed
 230
 231 X-Form
 232
 233 * ldupx RT,RA,RB
 234
 235 Pseudo-code:
 236
 237     EA <- (RA)
 238     RT <- MEM(EA, 8)
 239     RA <- (RA) + (RB)
 240
 241 Special Registers Altered:
 242
 243     None
 244