openpower/isa/pifixedload.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update
  12
  13 D-Form
  14
  15 * lbzup RT,D(RA)
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + EXTS(D)
  22
  23 Description:
  24
  25     Let the effective address (EA) be register RA.
  26     The byte in storage addressed by EA is loaded into RT[56:63].
  27     RT[0:55] are set to 0.
  28
  29     The sum (RA) + D is placed into register RA.
  30
  31     If RA=0 or RA=RT, the instruction form is invalid.
  32
  33 Special Registers Altered:
  34
  35     None
  36
  37 # Load Byte and Zero with Post-Update Indexed
  38
  39 X-Form
  40
  41 * lbzupx RT,RA,RB
  42
  43 Pseudo-code:
  44
  45     EA <- (RA)
  46     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  47     RA <- (RA) + (RB)
  48
  49 Description:
  50
  51     Let the effective address (EA) be register RA.
  52     The byte in storage addressed by EA is loaded into RT[56:63].
  53     RT[0:55] are set to 0.
  54
  55     The sum (RA) + (RB) is placed into register RA.
  56
  57     If RA=0 or RA=RT, the instruction form is invalid.
  58
  59 Special Registers Altered:
  60
  61     None
  62
  63 # Load Halfword and Zero with Post-Update
  64
  65 D-Form
  66
  67 * lhzup RT,D(RA)
  68
  69 Pseudo-code:
  70
  71     EA <- (RA)
  72     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  73     RA <- (RA) + EXTS(D)
  74
  75 Description:
  76
  77     Let the effective address (EA) be register RA.
  78     The halfword in storage addressed by EA is loaded into RT[48:63].
  79     RT[0:47] are set to 0.
  80
  81     The sum (RA) + D is placed into register RA.
  82
  83     If RA=0 or RA=RT, the instruction form is invalid.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Halfword and Zero with Post-Update Indexed
  90
  91 X-Form
  92
  93 * lhzupx RT,RA,RB
  94
  95 Pseudo-code:
  96
  97     EA <- (RA)
  98     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  99     RA <- (RA) + (RB)
 100
 101 Description:
 102
 103     Let the effective address (EA) be register RA.
 104     The halfword in storage addressed by EA is loaded into RT[48:63].
 105     RT[0:47] are set to 0.
 106
 107     The sum (RA) + (RB) is placed into register RA.
 108
 109     If RA=0 or RA=RT, the instruction form is invalid.
 110
 111 Special Registers Altered:
 112
 113     None
 114
 115 # Load Halfword Algebraic with Post-Update
 116
 117 D-Form
 118
 119 * lhaup RT,D(RA)
 120
 121 Pseudo-code:
 122
 123     EA <- (RA)
 124     RT <- EXTS(MEM(EA, 2))
 125     RA <- (RA) + EXTS(D)
 126
 127 Description:
 128
 129     Let the effective address (EA) be the register RA.
 130     The halfword in storage addressed by EA is loaded into RT[48:63].
 131     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 132
 133     The sum (RA) + D is placed into register RA.
 134
 135     If RA=0 or RA=RT, the instruction form is invalid.
 136
 137 Special Registers Altered:
 138
 139     None
 140
 141 # Load Halfword Algebraic with Post-Update Indexed
 142
 143 X-Form
 144
 145 * lhaupx RT,RA,RB
 146
 147 Pseudo-code:
 148
 149     EA <- (RA)
 150     RT <- EXTS(MEM(EA, 2))
 151     RA <- (RA) + (RB)
 152
 153 Description:
 154
 155     Let the effective address (EA) be the register RA.
 156     The halfword in storage addressed by EA is loaded into RT[48:63].
 157     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 158
 159     The sum (RA) + (RB) is placed into register RA.
 160
 161     If RA=0 or RA=RT, the instruction form is invalid.
 162
 163 Special Registers Altered:
 164
 165     None
 166
 167 # Load Word and Zero with Post-Update
 168
 169 D-Form
 170
 171 * lwzup RT,D(RA)
 172
 173 Pseudo-code:
 174
 175     EA <- (RA)
 176     RT <- [0]*32 || MEM(EA, 4)
 177     RA <- (RA) + EXTS(D)
 178
 179 Description:
 180
 181     Let the effective address (EA) be the register RA.
 182     The halfword in storage addressed by EA is loaded into RT[48:63].
 183     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 184
 185     The sum (RA) + D is placed into register RA.
 186
 187     If RA=0 or RA=RT, the instruction form is invalid.
 188
 189
 190 Special Registers Altered:
 191
 192     None
 193
 194 # Load Word and Zero with Post-Update Indexed
 195
 196 X-Form
 197
 198 * lwzupx RT,RA,RB
 199
 200 Pseudo-code:
 201
 202     EA <- (RA)
 203     RT <- [0] * 32 || MEM(EA, 4)
 204     RA <- (RA) + (RB)
 205
 206 Special Registers Altered:
 207
 208     None
 209
 210 # Load Word Algebraic with Post-Update Indexed
 211
 212 X-Form
 213
 214 * lwaupx RT,RA,RB
 215
 216 Pseudo-code:
 217
 218     EA <- (RA)
 219     RT <- EXTS(MEM(EA, 4))
 220     RA <- (RA) + (RB)
 221
 222 Special Registers Altered:
 223
 224     None
 225
 226 # Load Doubleword with Post-Update Indexed
 227
 228 DS-Form
 229
 230 * ldup RT,DS(RA)
 231
 232 Pseudo-code:
 233
 234     EA <- (RA)
 235     RT <- MEM(EA, 8)
 236     RA <- (RA) + EXTS(DS || 0b00)
 237
 238 Special Registers Altered:
 239
 240     None
 241
 242 # Load Doubleword with Post-Update Indexed
 243
 244 X-Form
 245
 246 * ldupx RT,RA,RB
 247
 248 Pseudo-code:
 249
 250     EA <- (RA)
 251     RT <- MEM(EA, 8)
 252     RA <- (RA) + (RB)
 253
 254 Special Registers Altered:
 255
 256     None
 257