openpower/isa/pifixedload.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update
  12
  13 D-Form
  14
  15 * lbzup RT,D(RA)
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + EXTS(D)
  22
  23 Description:
  24
  25     Let the effective address (EA) be register RA.
  26     The byte in storage addressed by EA is loaded into RT[56:63].
  27     RT[0:55] are set to 0.
  28
  29     The sum (RA) + D is placed into register RA.
  30
  31     If RA=0 or RA=RT, the instruction form is invalid.
  32
  33 Special Registers Altered:
  34
  35     None
  36
  37 # Load Byte and Zero with Post-Update Indexed
  38
  39 X-Form
  40
  41 * lbzupx RT,RA,RB
  42
  43 Pseudo-code:
  44
  45     EA <- (RA)
  46     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  47     RA <- (RA) + (RB)
  48
  49 Description:
  50
  51     Let the effective address (EA) be register RA.
  52     The byte in storage addressed by EA is loaded into RT[56:63].
  53     RT[0:55] are set to 0.
  54
  55     The sum (RA) + (RB) is placed into register RA.
  56
  57     If RA=0 or RA=RT, the instruction form is invalid.
  58
  59 Special Registers Altered:
  60
  61     None
  62
  63 # Load Halfword and Zero with Post-Update
  64
  65 D-Form
  66
  67 * lhzup RT,D(RA)
  68
  69 Pseudo-code:
  70
  71     EA <- (RA)
  72     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  73     RA <- (RA) + EXTS(D)
  74
  75 Description:
  76
  77     Let the effective address (EA) be register RA.
  78     The halfword in storage addressed by EA is loaded into RT[48:63].
  79     RT[0:47] are set to 0.
  80
  81     The sum (RA) + D is placed into register RA.
  82
  83     If RA=0 or RA=RT, the instruction form is invalid.
  84
  85 Special Registers Altered:
  86
  87     None
  88
  89 # Load Halfword and Zero with Post-Update Indexed
  90
  91 X-Form
  92
  93 * lhzupx RT,RA,RB
  94
  95 Pseudo-code:
  96
  97     EA <- (RA)
  98     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  99     RA <- (RA) + (RB)
 100
 101 Description:
 102
 103     Let the effective address (EA) be register RA.
 104     The halfword in storage addressed by EA is loaded into RT[48:63].
 105     RT[0:47] are set to 0.
 106
 107     The sum (RA) + (RB) is placed into register RA.
 108
 109     If RA=0 or RA=RT, the instruction form is invalid.
 110
 111 Special Registers Altered:
 112
 113     None
 114
 115 # Load Halfword Algebraic with Post-Update
 116
 117 D-Form
 118
 119 * lhaup RT,D(RA)
 120
 121 Pseudo-code:
 122
 123     EA <- (RA)
 124     RT <- EXTS(MEM(EA, 2))
 125     RA <- (RA) + EXTS(D)
 126
 127 Description:
 128
 129     Let the effective address (EA) be the register RA.
 130     The halfword in storage addressed by EA is loaded into RT[48:63].
 131     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 132
 133 Special Registers Altered:
 134
 135     None
 136
 137 # Load Halfword Algebraic with Post-Update Indexed
 138
 139 X-Form
 140
 141 * lhaupx RT,RA,RB
 142
 143 Pseudo-code:
 144
 145     EA <- (RA)
 146     RT <- EXTS(MEM(EA, 2))
 147     RA <- (RA) + (RB)
 148
 149 Description:
 150
 151     Let the effective address (EA) be the register RA.
 152     The halfword in storage addressed by EA is loaded into RT[48:63].
 153     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 154
 155 Special Registers Altered:
 156
 157     None
 158
 159 # Load Word and Zero with Post-Update
 160
 161 D-Form
 162
 163 * lwzup RT,D(RA)
 164
 165 Pseudo-code:
 166
 167     EA <- (RA)
 168     RT <- [0]*32 || MEM(EA, 4)
 169     RA <- (RA) + EXTS(D)
 170
 171 Special Registers Altered:
 172
 173     None
 174
 175 # Load Word and Zero with Post-Update Indexed
 176
 177 X-Form
 178
 179 * lwzupx RT,RA,RB
 180
 181 Pseudo-code:
 182
 183     EA <- (RA)
 184     RT <- [0] * 32 || MEM(EA, 4)
 185     RA <- (RA) + (RB)
 186
 187 Special Registers Altered:
 188
 189     None
 190
 191 # Load Word Algebraic with Post-Update Indexed
 192
 193 X-Form
 194
 195 * lwaupx RT,RA,RB
 196
 197 Pseudo-code:
 198
 199     EA <- (RA)
 200     RT <- EXTS(MEM(EA, 4))
 201     RA <- (RA) + (RB)
 202
 203 Special Registers Altered:
 204
 205     None
 206
 207 # Load Doubleword with Post-Update Indexed
 208
 209 DS-Form
 210
 211 * ldup RT,DS(RA)
 212
 213 Pseudo-code:
 214
 215     EA <- (RA)
 216     RT <- MEM(EA, 8)
 217     RA <- (RA) + EXTS(DS || 0b00)
 218
 219 Special Registers Altered:
 220
 221     None
 222
 223 # Load Doubleword with Post-Update Indexed
 224
 225 X-Form
 226
 227 * ldupx RT,RA,RB
 228
 229 Pseudo-code:
 230
 231     EA <- (RA)
 232     RT <- MEM(EA, 8)
 233     RA <- (RA) + (RB)
 234
 235 Special Registers Altered:
 236
 237     None
 238