openpower/isa/pifixedloadshift.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update Indexed
  12
  13 X-Form
  14
  15 * lbzupx RT,RA,RB
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + (RB)
  22
  23 Description:
  24
  25     Let the effective address (EA) be register RA.
  26
  27     The byte in storage addressed by EA is loaded into RT[56:63].
  28     RT[0:55] are set to 0.
  29
  30     The sum (RA) + (RB) is placed into register RA.
  31
  32     If RA=0 or RA=RT, the instruction form is invalid.
  33
  34 Special Registers Altered:
  35
  36     None
  37
  38 # Load Halfword and Zero with Post-Update Indexed
  39
  40 X-Form
  41
  42 * lhzupx RT,RA,RB
  43
  44 Pseudo-code:
  45
  46     EA <- (RA)
  47     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  48     RA <- (RA) + (RB)
  49
  50 Description:
  51
  52     Let the effective address (EA) be register RA.
  53     The halfword in storage addressed by EA is loaded into RT[48:63].
  54     RT[0:47] are set to 0.
  55
  56     The sum (RA) + (RB) is placed into register RA.
  57
  58     If RA=0 or RA=RT, the instruction form is invalid.
  59
  60 Special Registers Altered:
  61
  62     None
  63
  64 # Load Halfword Algebraic with Post-Update
  65
  66 D-Form
  67
  68 * lhaup RT,D(RA)
  69
  70 Pseudo-code:
  71
  72     EA <- (RA)
  73     RT <- EXTS(MEM(EA, 2))
  74     RA <- (RA) + EXTS(D)
  75
  76 Description:
  77
  78     Let the effective address (EA) be the register RA.
  79
  80     The halfword in storage addressed by EA is loaded into RT[48:63].
  81     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
  82
  83     The sum (RA) + D is placed into register RA.
  84
  85     If RA=0 or RA=RT, the instruction form is invalid.
  86
  87 Special Registers Altered:
  88
  89     None
  90
  91 # Load Halfword Algebraic with Post-Update Indexed
  92
  93 X-Form
  94
  95 * lhaupx RT,RA,RB
  96
  97 Pseudo-code:
  98
  99     EA <- (RA)
 100     RT <- EXTS(MEM(EA, 2))
 101     RA <- (RA) + (RB)
 102
 103 Description:
 104
 105     Let the effective address (EA) be the register RA.
 106
 107     The halfword in storage addressed by EA is loaded into RT[48:63].
 108     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 109
 110     The sum (RA) + (RB) is placed into register RA.
 111
 112     If RA=0 or RA=RT, the instruction form is invalid.
 113
 114 Special Registers Altered:
 115
 116     None
 117
 118 # Load Word and Zero with Post-Update Indexed
 119
 120 X-Form
 121
 122 * lwzupx RT,RA,RB
 123
 124 Pseudo-code:
 125
 126     EA <- (RA)
 127     RT <- [0] * 32 || MEM(EA, 4)
 128     RA <- (RA) + (RB)
 129
 130 Description:
 131
 132     Let the effective address (EA) be the register RA.
 133
 134     The halfword in storage addressed by EA is loaded into RT[48:63].
 135     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 136
 137     The sum (RA) + (RB) is placed into register RA.
 138
 139     If RA=0 or RA=RT, the instruction form is invalid.
 140
 141 Special Registers Altered:
 142
 143     None
 144
 145 # Load Word Algebraic with Post-Update Indexed
 146
 147 X-Form
 148
 149 * lwaupx RT,RA,RB
 150
 151 Pseudo-code:
 152
 153     EA <- (RA)
 154     RT <- EXTS(MEM(EA, 4))
 155     RA <- (RA) + (RB)
 156
 157 Description:
 158
 159     Let the effective address (EA) be the register RA.
 160
 161     The word in storage addressed by EA is loaded into RT[32:63].
 162     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 163
 164     The sum (RA) + (RB) is placed into register RA.
 165
 166     If RA=0 or RA=RT, the instruction form is invalid.
 167
 168 Special Registers Altered:
 169
 170     None
 171
 172 # Load Doubleword with Post-Update Indexed
 173
 174 X-Form
 175
 176 * ldupx RT,RA,RB
 177
 178 Pseudo-code:
 179
 180     EA <- (RA)
 181     RT <- MEM(EA, 8)
 182     RA <- (RA) + (RB)
 183
 184 Description:
 185
 186     Let the effective address (EA) be the register RA.
 187
 188     The doubleword in storage addressed by EA is loaded into RT.
 189
 190     The sum (RA) + (RB) is placed into register RA.
 191
 192     If RA=0 or RA=RT, the instruction form is invalid.
 193
 194 Special Registers Altered:
 195
 196     None
 197