openpower/isa/pifixedloadshift.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstoreshift.mdwn -->
   8 <!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
   9 <!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
  10
  11
  12
  13
  14 # Load Byte and Zero with Post-Update Indexed
  15
  16 Z23-Form
  17
  18 * lbzupsx RT,RA,RB,SH
  19
  20 Pseudo-code:
  21
  22     EA <- (RA)<<(SH+1)
  23     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  24     RA <- (RA) + (RB)
  25
  26 Description:
  27
  28     Let the effective address (EA) be the sum of the contents of
  29     register RB shifted by (SH+1), and the contents of register RA.
  30
  31     The byte in storage addressed by EA is loaded into RT[56:63].
  32     RT[0:55] are set to 0.
  33
  34     The sum (RA) + (RB) is placed into register RA.
  35
  36     If RA=0 or RA=RT, the instruction form is invalid.
  37
  38 Special Registers Altered:
  39
  40     None
  41
  42 # Load Halfword and Zero with Post-Update Indexed
  43
  44 Z23-Form
  45
  46 * lhzupsx RT,RA,RB
  47
  48 Pseudo-code:
  49
  50     EA <- (RA)
  51     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  52     RA <- (RA) + (RB)
  53
  54 Description:
  55
  56     Let the effective address (EA) be register RA.
  57     The halfword in storage addressed by EA is loaded into RT[48:63].
  58     RT[0:47] are set to 0.
  59
  60     The sum (RA) + (RB) is placed into register RA.
  61
  62     If RA=0 or RA=RT, the instruction form is invalid.
  63
  64 Special Registers Altered:
  65
  66     None
  67
  68 # Load Halfword Algebraic with Post-Update Indexed
  69
  70 Z23-Form
  71
  72 * lhaupsx RT,RA,RB
  73
  74 Pseudo-code:
  75
  76     EA <- (RA)
  77     RT <- EXTS(MEM(EA, 2))
  78     RA <- (RA) + (RB)
  79
  80 Description:
  81
  82     Let the effective address (EA) be the register RA.
  83
  84     The halfword in storage addressed by EA is loaded into RT[48:63].
  85     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
  86
  87     The sum (RA) + (RB) is placed into register RA.
  88
  89     If RA=0 or RA=RT, the instruction form is invalid.
  90
  91 Special Registers Altered:
  92
  93     None
  94
  95 # Load Word and Zero with Post-Update Indexed
  96
  97 Z23-Form
  98
  99 * lwzupsx RT,RA,RB
 100
 101 Pseudo-code:
 102
 103     EA <- (RA)
 104     RT <- [0] * 32 || MEM(EA, 4)
 105     RA <- (RA) + (RB)
 106
 107 Description:
 108
 109     Let the effective address (EA) be the register RA.
 110
 111     The halfword in storage addressed by EA is loaded into RT[48:63].
 112     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
 113
 114     The sum (RA) + (RB) is placed into register RA.
 115
 116     If RA=0 or RA=RT, the instruction form is invalid.
 117
 118 Special Registers Altered:
 119
 120     None
 121
 122 # Load Word Algebraic with Post-Update Indexed
 123
 124 Z23-Form
 125
 126 * lwaupsx RT,RA,RB
 127
 128 Pseudo-code:
 129
 130     EA <- (RA)
 131     RT <- EXTS(MEM(EA, 4))
 132     RA <- (RA) + (RB)
 133
 134 Description:
 135
 136     Let the effective address (EA) be the register RA.
 137
 138     The word in storage addressed by EA is loaded into RT[32:63].
 139     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 140
 141     The sum (RA) + (RB) is placed into register RA.
 142
 143     If RA=0 or RA=RT, the instruction form is invalid.
 144
 145 Special Registers Altered:
 146
 147     None
 148
 149 # Load Doubleword with Post-Update Indexed
 150
 151 Z23-Form
 152
 153 * ldupsx RT,RA,RB
 154
 155 Pseudo-code:
 156
 157     EA <- (RA)
 158     RT <- MEM(EA, 8)
 159     RA <- (RA) + (RB)
 160
 161 Description:
 162
 163     Let the effective address (EA) be the register RA.
 164
 165     The doubleword in storage addressed by EA is loaded into RT.
 166
 167     The sum (RA) + (RB) is placed into register RA.
 168
 169     If RA=0 or RA=RT, the instruction form is invalid.
 170
 171 Special Registers Altered:
 172
 173     None
 174