1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
3 <!-- This defines instructions that load from RAM to a register -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 <!-- Note that these pages also define equivalent store instructions, -->
7 <!-- these are described in pifixedstoreshift.mdwn -->
8 <!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
9 <!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
14 # Load Byte and Zero with Post-Update Indexed
23 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
28 Let the effective address (EA) be the contents of
29 register RA shifted by (SH+1).
31 The byte in storage addressed by EA is loaded into RT[56:63].
32 RT[0:55] are set to 0.
34 The sum (RA) + (RB) is placed into register RA.
36 If RA=0 or RA=RT, the instruction form is invalid.
38 Special Registers Altered:
42 # Load Halfword and Zero with Post-Update Indexed
51 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
56 Let the effective address (EA) be the contents of
57 register RA shifted by (SH+1).
59 The halfword in storage addressed by EA is loaded into RT[48:63].
60 RT[0:47] are set to 0.
62 The sum (RA) + (RB) is placed into register RA.
64 If RA=0 or RA=RT, the instruction form is invalid.
66 Special Registers Altered:
70 # Load Halfword Algebraic with Post-Update Indexed
79 RT <- EXTS(MEM(EA, 2))
84 Let the effective address (EA) be the contents of
85 register RA shifted by (SH+1).
87 The halfword in storage addressed by EA is loaded into RT[48:63].
88 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
90 The sum (RA) + (RB) is placed into register RA.
92 If RA=0 or RA=RT, the instruction form is invalid.
94 Special Registers Altered:
98 # Load Word and Zero with Post-Update Indexed
102 * lwzupsx RT,RA,RB,SH
107 RT <- [0] * 32 || MEM(EA, 4)
112 Let the effective address (EA) be the contents of
113 register RA shifted by (SH+1).
115 The halfword in storage addressed by EA is loaded into RT[48:63].
116 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
118 The sum (RA) + (RB) is placed into register RA.
120 If RA=0 or RA=RT, the instruction form is invalid.
122 Special Registers Altered:
126 # Load Word Algebraic with Post-Update Indexed
130 * lwaupsx RT,RA,RB.SH
135 RT <- EXTS(MEM(EA, 4))
140 Let the effective address (EA) be the contents of
141 register RA shifted by (SH+1).
143 The word in storage addressed by EA is loaded into RT[32:63].
144 RT[0:31] are filled with a copy of bit 0 of the loaded word.
146 The sum (RA) + (RB) is placed into register RA.
148 If RA=0 or RA=RT, the instruction form is invalid.
150 Special Registers Altered:
154 # Load Doubleword with Post-Update Indexed
168 Let the effective address (EA) be the contents of
169 register RA shifted by (SH+1).
171 The doubleword in storage addressed by EA is loaded into RT.
173 The sum (RA) + (RB) is placed into register RA.
175 If RA=0 or RA=RT, the instruction form is invalid.
177 Special Registers Altered: