openpower/isa/pifixedstore.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Post-Update
   7
   8 D-Form
   9
  10 * stbup RS,D(RA)
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + EXTS(D)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Description:
  20
  21     Let the effective address (EA) be the sum (RA)+ D.
  22
  23     (RS)[56:63] are stored into the byte in storage addressed
  24     by RA.
  25
  26     EA is placed into register RA.
  27
  28     If RA=0, the instruction form is invalid.
  29
  30 Special Registers Altered:
  31
  32     None
  33
  34 # Store Byte with Post-Update Indexed
  35
  36 X-Form
  37
  38 * stbupx RS,RA,RB
  39
  40 Pseudo-code:
  41
  42     EA <- (RA) + (RB)
  43     ea <- (RA)
  44     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  45     RA <- EA
  46
  47 Description:
  48
  49     Let the effective address (EA) be the sum (RA)+ (RB).
  50
  51     (RS)[56:63] are stored into the byte in storage addressed
  52     by EA.
  53
  54     EA is placed into register RA.
  55
  56     If RA=0, the instruction form is invalid.
  57
  58 Special Registers Altered:
  59
  60     None
  61
  62 # Store Halfword with Post-Update
  63
  64 D-Form
  65
  66 * sthup RS,D(RA)
  67
  68 Pseudo-code:
  69
  70     EA <- (RA) + EXTS(D)
  71     ea <- (RA)
  72     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  73     RA <- EA
  74
  75 Description:
  76
  77     Let the effective address (EA) be the sum (RA|0)+ D.
  78
  79     (RS)[48:63] are stored into the halfword in storage
  80     addressed by EA.
  81
  82 Special Registers Altered:
  83
  84     None
  85
  86 # Store Halfword with Post-Update Indexed
  87
  88 X-Form
  89
  90 * sthupx RS,RA,RB
  91
  92 Pseudo-code:
  93
  94     EA <- (RA) + (RB)
  95     ea <- (RA)
  96     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  97     RA <- EA
  98
  99 Description:
 100
 101     Let the effective address (EA) be the sum (RA)+ (RB).
 102
 103     (RS)[56:63] are stored into the byte in storage addressed
 104     by EA.
 105
 106     EA is placed into register RA.
 107
 108     If RA=0, the instruction form is invalid
 109
 110 Special Registers Altered:
 111
 112     None
 113
 114 # Store Word with Post-Update
 115
 116 D-Form
 117
 118 * stwup RS,D(RA)
 119
 120 Pseudo-code:
 121
 122     EA <- (RA) + EXTS(D)
 123     ea <- (RA)
 124     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 125     RA <- EA
 126
 127 Description:
 128
 129     Let the effective address (EA) be the sum (RA)+ D.
 130
 131     (RS)[32:63] are stored into the word in storage addressed
 132     by EA.
 133
 134     EA is placed into register RA.
 135
 136     If RA=0, the instruction form is invalid.
 137
 138 Special Registers Altered:
 139
 140     None
 141
 142 # Store Word with Post-Update Indexed
 143
 144 X-Form
 145
 146 * stwupx RS,RA,RB
 147
 148 Pseudo-code:
 149
 150     EA <- (RA) + (RB)
 151     ea <- (RA)
 152     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 153     RA <- EA
 154
 155 Description:
 156
 157     Let the effective address (EA) be the sum (RA)+ (RB).
 158
 159     (RS)[32:63] are stored into the word in storage addressed
 160     by RA.
 161
 162     EA is placed into register RA.
 163
 164     If RA=0, the instruction form is invalid.
 165
 166 Special Registers Altered:
 167
 168     None
 169
 170 # Store Doubleword with Post-Update
 171
 172 DS-Form
 173
 174 * stdup RS,DS(RA)
 175
 176 Pseudo-code:
 177
 178     EA <- (RA) + EXTS(DS || 0b00)
 179     ea <- (RA)
 180     MEM(ea, 8) <- (RS)
 181     RA <- EA
 182
 183 Description:
 184
 185     Let the effective address (EA) be the sum.
 186
 187     (RA)+ (DS||0b00). (RS) is stored into the doubleword in
 188     storage addressed by RA.
 189
 190     EA is placed into register RA.
 191
 192     If RA=0, the instruction form is invalid.
 193
 194 Special Registers Altered:
 195
 196     None
 197
 198 # Store Doubleword with Post-Update Indexed
 199
 200 X-Form
 201
 202 * stdupx RS,RA,RB
 203
 204 Pseudo-code:
 205
 206     EA <- (RA) + (RB)
 207     ea <- (RA)
 208     MEM(ea, 8) <- (RS)
 209     RA <- EA
 210
 211 Description:
 212
 213     Let the effective address (EA) be the sum (RA)+ (RB).
 214
 215     (RS) is stored into the doubleword in storage
 216     addressed by RA.
 217
 218     EA is placed into register RA.
 219
 220     If RA=0, the instruction form is invalid.
 221
 222 Special Registers Altered:
 223
 224     None
 225