openpower/isa/pifixedstore.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Update
   7
   8 D-Form
   9
  10 * stbup RS,D(RA)
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + EXTS(D)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Description:
  20
  21     Let the effective address (EA) be the sum (RA)+ D.
  22     (RS)[56:63] are stored into the byte in storage addressed
  23     by EA.
  24
  25     EA is placed into register RA.
  26
  27     If RA=0, the instruction form is invalid.
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Byte with Update Indexed
  34
  35 X-Form
  36
  37 * stbupx RS,RA,RB
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + (RB)
  42     ea <- (RA)
  43     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  44     RA <- EA
  45
  46 Description:
  47
  48     Let the effective address (EA) be the sum (RA)+ (RB).
  49     (RS)[56:63] are stored into the byte in storage addressed
  50     by EA.
  51
  52     EA is placed into register RA.
  53
  54     If RA=0, the instruction form is invalid.
  55
  56 Special Registers Altered:
  57
  58     None
  59
  60 # Store Halfword with Update
  61
  62 D-Form
  63
  64 * sthup RS,D(RA)
  65
  66 Pseudo-code:
  67
  68     EA <- (RA) + EXTS(D)
  69     ea <- (RA)
  70     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  71     RA <- EA
  72
  73 Special Registers Altered:
  74
  75     None
  76
  77 # Store Halfword with Update Indexed
  78
  79 X-Form
  80
  81 * sthupx RS,RA,RB
  82
  83 Pseudo-code:
  84
  85     EA <- (RA) + (RB)
  86     ea <- (RA)
  87     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  88     RA <- EA
  89
  90 Special Registers Altered:
  91
  92     None
  93
  94 # Store Word with Update
  95
  96 D-Form
  97
  98 * stwup RS,D(RA)
  99
 100 Pseudo-code:
 101
 102     EA <- (RA) + EXTS(D)
 103     ea <- (RA)
 104     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 105     RA <- EA
 106
 107 Special Registers Altered:
 108
 109     None
 110
 111 # Store Word with Update Indexed
 112
 113 X-Form
 114
 115 * stwupx RS,RA,RB
 116
 117 Pseudo-code:
 118
 119     EA <- (RA) + (RB)
 120     ea <- (RA)
 121     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 122     RA <- EA
 123
 124 Special Registers Altered:
 125
 126     None
 127
 128 # Store Doubleword with Update
 129
 130 DS-Form
 131
 132 * stdup RS,DS(RA)
 133
 134 Pseudo-code:
 135
 136     EA <- (RA) + EXTS(DS || 0b00)
 137     ea <- (RA)
 138     MEM(ea, 8) <- (RS)
 139     RA <- EA
 140
 141 Special Registers Altered:
 142
 143     None
 144
 145 # Store Doubleword with Update Indexed
 146
 147 X-Form
 148
 149 * stdupx RS,RA,RB
 150
 151 Pseudo-code:
 152
 153     EA <- (RA) + (RB)
 154     ea <- (RA)
 155     MEM(ea, 8) <- (RS)
 156     RA <- EA
 157
 158 Special Registers Altered:
 159
 160     None
 161