openpower/isa/pifixedstore.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Update
   7
   8 D-Form
   9
  10 * stbup RS,D(RA)
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + EXTS(D)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Description:
  20
  21     Let the effective address (EA) be the sum (RA)+ D.
  22     (RS)[56:63] are stored into the byte in storage addressed
  23     by EA.
  24
  25     EA is placed into register RA.
  26
  27     If RA=0, the instruction form is invalid.
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Byte with Update Indexed
  34
  35 X-Form
  36
  37 * stbupx RS,RA,RB
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + (RB)
  42     ea <- (RA)
  43     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  44     RA <- EA
  45
  46 Special Registers Altered:
  47
  48     None
  49
  50 # Store Halfword with Update
  51
  52 D-Form
  53
  54 * sthup RS,D(RA)
  55
  56 Pseudo-code:
  57
  58     EA <- (RA) + EXTS(D)
  59     ea <- (RA)
  60     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  61     RA <- EA
  62
  63 Special Registers Altered:
  64
  65     None
  66
  67 # Store Halfword with Update Indexed
  68
  69 X-Form
  70
  71 * sthupx RS,RA,RB
  72
  73 Pseudo-code:
  74
  75     EA <- (RA) + (RB)
  76     ea <- (RA)
  77     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  78     RA <- EA
  79
  80 Special Registers Altered:
  81
  82     None
  83
  84 # Store Word with Update
  85
  86 D-Form
  87
  88 * stwup RS,D(RA)
  89
  90 Pseudo-code:
  91
  92     EA <- (RA) + EXTS(D)
  93     ea <- (RA)
  94     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
  95     RA <- EA
  96
  97 Special Registers Altered:
  98
  99     None
 100
 101 # Store Word with Update Indexed
 102
 103 X-Form
 104
 105 * stwupx RS,RA,RB
 106
 107 Pseudo-code:
 108
 109     EA <- (RA) + (RB)
 110     ea <- (RA)
 111     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 112     RA <- EA
 113
 114 Special Registers Altered:
 115
 116     None
 117
 118 # Store Doubleword with Update
 119
 120 DS-Form
 121
 122 * stdup RS,DS(RA)
 123
 124 Pseudo-code:
 125
 126     EA <- (RA) + EXTS(DS || 0b00)
 127     ea <- (RA)
 128     MEM(ea, 8) <- (RS)
 129     RA <- EA
 130
 131 Special Registers Altered:
 132
 133     None
 134
 135 # Store Doubleword with Update Indexed
 136
 137 X-Form
 138
 139 * stdupx RS,RA,RB
 140
 141 Pseudo-code:
 142
 143     EA <- (RA) + (RB)
 144     ea <- (RA)
 145     MEM(ea, 8) <- (RS)
 146     RA <- EA
 147
 148 Special Registers Altered:
 149
 150     None
 151