openpower/isa/pifixedstore.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Update
   7
   8 D-Form
   9
  10 * stbup RS,D(RA)
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + EXTS(D)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Description:
  20
  21     Let the effective address (EA) be the sum (RA)+ D.
  22     (RS)[56:63] are stored into the byte in storage addressed
  23     by EA.
  24
  25     EA is placed into register RA.
  26
  27     If RA=0, the instruction form is invalid.
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Byte with Update Indexed
  34
  35 X-Form
  36
  37 * stbupx RS,RA,RB
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + (RB)
  42     ea <- (RA)
  43     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  44     RA <- EA
  45
  46 Description:
  47
  48     Let the effective address (EA) be the sum (RA)+ (RB).
  49     (RS)[56:63] are stored into the byte in storage addressed
  50     by EA.
  51
  52     EA is placed into register RA.
  53
  54     If RA=0, the instruction form is invalid.
  55
  56 Special Registers Altered:
  57
  58     None
  59
  60 # Store Halfword with Update
  61
  62 D-Form
  63
  64 * sthup RS,D(RA)
  65
  66 Pseudo-code:
  67
  68     EA <- (RA) + EXTS(D)
  69     ea <- (RA)
  70     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  71     RA <- EA
  72
  73 Description:
  74
  75     Let the effective address (EA) be the sum (RA|0)+ D.
  76     (RS)[48:63] are stored into the halfword in storage
  77     addressed by EA.
  78
  79 Special Registers Altered:
  80
  81     None
  82
  83 # Store Halfword with Update Indexed
  84
  85 X-Form
  86
  87 * sthupx RS,RA,RB
  88
  89 Pseudo-code:
  90
  91     EA <- (RA) + (RB)
  92     ea <- (RA)
  93     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  94     RA <- EA
  95
  96 Description:
  97
  98
  99
 100 Special Registers Altered:
 101
 102     None
 103
 104 # Store Word with Update
 105
 106 D-Form
 107
 108 * stwup RS,D(RA)
 109
 110 Pseudo-code:
 111
 112     EA <- (RA) + EXTS(D)
 113     ea <- (RA)
 114     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 115     RA <- EA
 116
 117 Special Registers Altered:
 118
 119     None
 120
 121 # Store Word with Update Indexed
 122
 123 X-Form
 124
 125 * stwupx RS,RA,RB
 126
 127 Pseudo-code:
 128
 129     EA <- (RA) + (RB)
 130     ea <- (RA)
 131     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 132     RA <- EA
 133
 134 Special Registers Altered:
 135
 136     None
 137
 138 # Store Doubleword with Update
 139
 140 DS-Form
 141
 142 * stdup RS,DS(RA)
 143
 144 Pseudo-code:
 145
 146     EA <- (RA) + EXTS(DS || 0b00)
 147     ea <- (RA)
 148     MEM(ea, 8) <- (RS)
 149     RA <- EA
 150
 151 Special Registers Altered:
 152
 153     None
 154
 155 # Store Doubleword with Update Indexed
 156
 157 X-Form
 158
 159 * stdupx RS,RA,RB
 160
 161 Pseudo-code:
 162
 163     EA <- (RA) + (RB)
 164     ea <- (RA)
 165     MEM(ea, 8) <- (RS)
 166     RA <- EA
 167
 168 Special Registers Altered:
 169
 170     None
 171